Noboru Tanabe

29 papers B 2C 5Misc 4Journal 7Unranked 11
YearRankTypeTitle / Venue / Authors
2018 C conf
Characterizing Memory-Latency Sensitivity of Sparse Matrix Kernels.
PDP
Noboru Tanabe, Toshio Endo
2018 — conf
Exhaustive evaluation of memory-latency sensitivity on manycore processors with large cache.
HP3C
Noboru Tanabe, Toshio Endo
2013 — conf
Character of Graph Analysis Workloads and Recommended Solutions on Future Parallel Systems.
ICA3PP (1)
Noboru Tanabe, Sonoko Tomimori, Masami Takata, Kazuki Joe
2013 J jnl
Network Interface Architecture with Scalable Low-Latency Message Receiving Mechanism.
IEICE Trans. Inf. Syst.
Noboru Tanabe, Atsushi Ohta
2011 — conf
A memory accelerator with gather functions for bandwidth-bound irregular applications.
IA3@SC
Noboru Tanabe, Boonyasitpichai Nuttapon, Hironori Nakajo, Yuka Ogawa, Junko Kogou, Masami Takata, Kazuki Joe
2011 C conf
Scaleable Sparse Matrix-Vector Multiplication with Functional Memory and GPUs.
PDP
Noboru Tanabe, Yuuka Ogawa, Masami Takata, Kazuki Joe
2010 — conf
Acceleration for MPI derived datatypes using an enhancer of memory and network.
IPDPS Workshops
Noboru Tanabe, Hironori Nakajo
2010 J jnl
An enhancer of memory and network for applications with large-capacity data and non-continuous data accessing.
J. Supercomput.
Noboru Tanabe, Hirotaka Hakozaki, Hiroshi Ando, Yasunori Dohi, Zhengzhe Luo, Hironori Nakajo
2009 B conf
Network Interface Architecture for Scalable Message Queue Processing.
ICPADS
Noboru Tanabe, Atsushi Ohta, Pulung Waskito, Hironori Nakajo
2009 Misc conf
The architecture of visualization system using memory with memory-side gathering and CPUs with DMA-type memory accessing.
PDPTA
Noboru Tanabe, Manami Sasaki, Hironori Nakajo, Masami Takata, Kazuki Joe
2008 C conf
An Enhancer of Memory and Network for Cluster and its Applications.
PDCAT
Noboru Tanabe, Hironori Nakajo
2008 — conf
Introduction to Acceleration for MPI Derived Datatypes Using an Enhancer of Memory and Network.
PVM/MPI
Noboru Tanabe, Hironori Nakajo
2007 Misc conf
Implementation and Evaluation of Multicast Mechanism on Network Interface Plugged into a Memory Slot.
PDPTA
Atsushi Ohta, Yoshihiro Hamada, Akira Kitamura, Noboru Tanabe, Hideharu Amano, Hironori Nakajo
2007 J jnl
Martini: A Network Interface Controller Chip for High Performance Computing with Distributed PCs.
IEEE Trans. Parallel Distributed Syst.
Konosuke Watanabe, Tomohiro Otsuka, Junichiro Tsuchiya, Hiroaki Nishi, Junji Yamamoto, Noboru Tanabe, Tomohiro Kudoh, Hideharu Amano
2007 — conf
Performance evaluation on low-latency communication mechanism of DIMMnet-2.
Parallel and Distributed Computing and Networks
Akira Kitamura, Yasuo Miyabe, Tomotaka Miyashiro, Noboru Tanabe, Hironori Nakajo, Hideharu Amano
2006 B conf
DIMMnet-2: A Reconfigurable Board Connected Into a Memory Slot.
FPL
Tomotaka Miyashiro, Akira Kitamura, Hironori Nakajo, Noboru Tanabe
2006 Misc conf
Implementation of PC Cluster System with Memory Mapped File by Commodity OS.
PDPTA
Jun Kanai, Takuro Mori, Takeshi Araki, Noboru Tanabe, Hironori Nakajo, Mitaro Namiki
2005 Misc conf
A Packet Forwarding Layer for DIMMnet and its Hardware Implementation.
PDPTA
Yoshihiro Hamada, Hiroaki Nishi, Akira Kitamura, Noboru Tanabe, Hideharu Amano, Hironori Nakajo
2005 C conf
Evaluation of Network Interface Controller on DIMMnet-2 Prototype Board.
PDCAT
Akira Kitamura, Yasuo Miyabe, Tetsu Izawa, Tomotaka Miyashiro, Konosuke Watanabe, Tomohiro Otsuka, Hideharu Amano, Yoshihiro Hamada, Noboru Tanabe, Hironori Nakajo
2005 — conf
Implementation and Evaluation of the Mechanisms for Low Latency Communication on DIMMnet-2.
ISHPC
Yasuo Miyabe, Akira Kitamura, Yoshihiro Hamada, Tomotaka Miyashiro, Tetsu Izawa, Noboru Tanabe, Hironori Nakajo, Hideharu Amano
2004 — conf
A New Memory Module for Memory Intensive Applications.
PARELEC
Noboru Tanabe, Hironori Nakajo, Hirotaka Hakozaki, Masasige Nakatake, Yasunori Dohi, Hideharu Amano
2002 — conf
Low Latency Communication on DIMMnet-1 Network Interface Plugged into a DIMM Slot.
PARELEC
Noboru Tanabe, Yoshihiro Hamada, Hironori Nakajo, Hideki Imashiro, Junji Yamamoto, Tomohiro Kudoh, Hideharu Amano
2002 J jnl
Low Latency High Bandwidth Message Transfer Mechanisms for a Network Interface Plugged into a Memory Slot.
Clust. Comput.
Noboru Tanabe, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano
2000 C conf
MEMOnet : Network interface plugged into a memory slot.
CLUSTER
Noboru Tanabe, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano
2000 — conf
On-the-fly Sending: A Low Latency High Bandwidth Message Transfer Mechanism.
ISPAN
Noboru Tanabe, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano
1996 J jnl
Improving the performance of global communication on a three-dimensional torus network.
Syst. Comput. Jpn.
Yasushi Kawakura, Noboru Tanabe, Shigeru Oyanagi
1992 J jnl
Implementation of the prodigy parallel AI machine and performance evaluation of communication.
Syst. Comput. Jpn.
Noboru Tanabe, Sadao Nakamura, Takashi Suzuoka, Shigeru Oyanagi
1991 — conf
Base-m n-cube: High Performance Interconnection Networks for Highly Parallel Computer PRODIGY.
ICPP (1)
Noboru Tanabe, Takashi Suzuoka, Sadao Nakamura, Yasushi Kawakura, Shigeru Oyanagi
1989 J jnl
Network Performance of the Prodigy Parallel AI Machine.
Syst. Comput. Jpn.
Takashi Suzuoka, Noboru Tanabe, Sadao Nakamura, Sumikazu Fujita, Shigeru Oyanagi