Noboru Sakimura

23 papers C 3Journal 14Unranked 6
YearRankTypeTitle / Venue / Authors
2016 J jnl
Evaluation of Soft-Delay-Error Effects in Content-Addressable Memory.
J. Multiple Valued Log. Soft Comput.
Naoya Onizawa, Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Takahiro Hanyu
2015 J jnl
Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction.
IEEE J. Solid State Circuits
Masanori Natsui, Daisuke Suzuki, Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Tadahiko Sugibayashi, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
2014 — conf
10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications.
ISSCC
Noboru Sakimura, Yukihide Tsuji, Ryusuke Nebashi, Hiroaki Honjo, Ayuka Morioka, Kunihiko Ishihara, Keizo Kinoshita, Shunsuke Fukami, Sadahiko Miura, Naoki Kasai, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu, Tadahiko Sugibayashi
2014 J jnl
A Nonvolatile Associative Memory-Based Context-Driven Search Engine Using 90 nm CMOS/MTJ-Hybrid Logic-in-Memory Architecture.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Hooman Jarollahi, Naoya Onizawa, Vincent Gripon, Noboru Sakimura, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu, Warren J. Gross
2014 J jnl
A compact low-power nonvolatile flip-flop using domain-wall-motion-device-based single-ended structure.
IEICE Electron. Express
Daisuke Suzuki, Noboru Sakimura, Masanori Natsui, Akira Mochizuki, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
2014 C conf
A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing.
ISCAS
Ryusuke Nebashi, Noboru Sakimura, Hiroaki Honjo, Ayuka Morioka, Yukihide Tsuji, Kunihiko Ishihara, Keiichi Tokutome, Sadahiko Miura, Shunsuke Fukami, Keizo Kinoshita, Takahiro Hanyu, Tetsuo Endoh, Naoki Kasai, Hideo Ohno, Tadahiko Sugibayashi
2014 J jnl
Complementary 5T-4MTJ nonvolatile TCAM cell circuit with phase-selective parallel writing scheme.
IEICE Electron. Express
Shoun Matsunaga, Akira Mochizuki, Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
2014 — conf
Soft-Delay-Error Evaluation in Content-Addressable Memory.
ISMVL
Naoya Onizawa, Shoun Matsunaga, Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Takahiro Hanyu
2013 J jnl
A Non-volatile Reconfigurable Offloader for Wireless Sensor Nodes.
Inf. Media Technol.
Shogo Nakaya, Makoto Miyamura, Noboru Sakimura, Yuichi Nakamura, Tadahiko Sugibayashi
2013 J jnl
A Non-volatile Reconfigurable Offloader for Wireless Sensor Nodes.
IPSJ Trans. Syst. LSI Des. Methodol.
Shogo Nakaya, Makoto Miyamura, Noboru Sakimura, Yuichi Nakamura, Tadahiko Sugibayashi
2013 C conf
MTJ/MOS-hybrid logic-circuit design flow for nonvolatile logic-in-memory LSI.
ISCAS
Masanori Natsui, Takahiro Hanyu, Noboru Sakimura, Tadahiko Sugibayashi
2013 — conf
Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating.
ISSCC
Masanori Natsui, Daisuke Suzuki, Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Tadahiko Sugibayashi, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
2012 J jnl
A non-volatile reconfigurable offloader for wireless sensor nodes.
SIGARCH Comput. Archit. News
Shogo Nakaya, Makoto Miyamura, Noboru Sakimura, Yuichi Nakamura, Tadahiko Sugibayashi
2012 C conf
High-speed simulator including accurate MTJ models for spintronics integrated circuit design.
ISCAS
Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Hiroaki Honjo, Tadahiko Sugibayashi, Hiroki Koike, Takashi Ohsawa, Shunsuke Fukami, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh
2011 — conf
Programmable cell array using rewritable solid-electrolyte switch integrated in 90nm CMOS.
ISSCC
Makoto Miyamura, Shogo Nakaya, Munehiro Tada, Toshitsugu Sakamoto, Koichiro Okamoto, Naoki Banno, Shinji Ishida, Kimihiko Ito, Hiromitsu Hada, Noboru Sakimura, Tadahiko Sugibayashi, Masato Motomura
2009 — conf
A 90nm 12ns 32Mb 2T1MTJ MRAM.
ISSCC
Ryusuke Nebashi, Noboru Sakimura, Hiroaki Honjo, Shinsaku Saito, Yuichi Ito, Sadahiko Miura, Yuko Kato, Kaoru Mori, Yasuaki Ozaki, Yosuke Kobayashi, Norikazu Ohshima, Keizo Kinoshita, Tetsuhiro Suzuki, Kiyokazu Nagahara, Nobuyuki Ishiwata, Katsumi Suemitsu, Shunsuke Fukami, Hiromitsu Hada, Tadahiko Sugibayashi, Naoki Kasai
2009 J jnl
Nonvolatile Magnetic Flip-Flop for Standby-Power-Free SoCs.
IEEE J. Solid State Circuits
Noboru Sakimura, Tadahiko Sugibayashi, Ryusuke Nebashi, Naoki Kasai
2009 J jnl
Shared Write-Selection Transistor Cell and Leakage-Replication Read Scheme for Large Capacity MRAM Macros.
IEICE Trans. Electron.
Ryusuke Nebashi, Noboru Sakimura, Tadahiko Sugibayashi, Naoki Kasai
2008 — conf
Nonvolatile Magnetic Flip-Flop for standby-power-free SoCs.
CICC
Noboru Sakimura, Tadahiko Sugibayashi, Ryusuke Nebashi, Naoki Kasai
2007 J jnl
A 16-Mb Toggle MRAM With Burst Modes.
IEEE J. Solid State Circuits
Tadahiko Sugibayashi, Noboru Sakimura, Takeshi Honda, Kiyokazu Nagahara, Kiyotaka Tsuji, Hideaki Numata, Sadahiko Miura, Ken-ichi Shimura, Yuko Kato, Shinsaku Saito, Yoshiyuki Fukumoto, Hiroaki Honjo, Tetsuhiro Suzuki, Katsumi Suemitsu, Tomonori Mukai, Kaoru Mori, Ryusuke Nebashi, Shunsuke Fukami, Norikazu Ohshima, Hiromitsu Hada, Nobuyuki Ishiwata, Naoki Kasai, Shuichi Tahara
2007 J jnl
MRAM Applications Using Unlimited Write Endurance.
IEICE Trans. Electron.
Tadahiko Sugibayashi, Takeshi Honda, Noboru Sakimura, Shuichi Tahara, Naoki Kasai
2007 J jnl
MRAM Cell Technology for Over 500-MHz SoC.
IEEE J. Solid State Circuits
Noboru Sakimura, Tadahiko Sugibayashi, Takeshi Honda, Hiroaki Honjo, Shinsaku Saito, Tetsuhiro Suzuki, Nobuyuki Ishiwata, Shuichi Tahara
2007 J jnl
Writing Circuitry for Toggle MRAM to Screen Intermittent Failure Mode.
IEICE Trans. Electron.
Takeshi Honda, Noboru Sakimura, Tadahiko Sugibayashi, Naoki Kasai, Hiromitsu Hada, Shuichi Tahara