Nitin Borkar

23 papers A 1Misc 3Journal 11Unranked 8
YearRankTypeTitle / Venue / Authors
2016 J jnl
System-Level Power Analysis of a Multicore Multipower Domain Processor With ON-Chip Voltage Regulators.
IEEE Trans. Very Large Scale Integr. Syst.
Ayan Paul, Sang Phill Park, Dinesh Somasekhar, Young Moon Kim, Nitin Borkar, Ulya R. Karpuzcu, Chris H. Kim
2014 — conf
Resiliency for many-core system on a chip.
ASP-DAC
Tanay Karnik, James W. Tschanz, Nitin Borkar, Jason Howard, Sriram R. Vangal, Vivek De, Shekhar Borkar
2012 — conf
A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS.
ISSCC
Shailendra Jain, Surhud Khare, Satish Yada, V. Ambili, Praveen Salihundam, Shiva Ramani, Sriram Muthukumar, M. Srinivasan, Arun Kumar, Shasi Kumar, Rajaraman Ramanarayanan, Vasantha Erraguntla, Jason Howard, Sriram R. Vangal, Saurabh Dighe, Gregory Ruhl, Paolo A. Aseron, Howard Wilson, Nitin Borkar, Vivek De, Shekhar Borkar
2012 Misc conf
A Reconfigurable On-die Traffic Generator in 45nm CMOS for a 48 iA-32 Core Network-on-Chip.
VLSI Design
Praveen Salihundam, Mohammed Asadullah Khan, Shailendra Jain, Yatin Vasant Hoskote, Satish Yada, Shasi Kumar, Vasantha Erraguntla, Sriram R. Vangal, Nitin Borkar
2012 — conf
An IA-32 processor with a wide voltage operating range in 32nm CMOS.
Hot Chips Symposium
Gregory Ruhl, Saurabh Dighe, Shailendra Jain, Surhud Khare, Satish Yada, V. Ambili, Praveen Salihundam, Shiva Ramani, Sriram Muthukumar, M. Srinivasan, Arun Kumar, Shasi Kumar, Rajaraman Ramanarayanan, Vasantha Erraguntla, Jason Howard, Sriram R. Vangal, Paolo A. Aseron, Howard Wilson, Nitin Borkar
2011 J jnl
A 2 Tb/s 6 , ˟, 4 Mesh Network for a Single-Chip Cloud Computer With DVFS in 45 nm CMOS.
IEEE J. Solid State Circuits
Praveen Salihundam, Shailendra Jain, Tiju Jacob, Shasi Kumar, Vasantha Erraguntla, Yatin Vasant Hoskote, Sriram R. Vangal, Gregory Ruhl, Nitin Borkar
2011 J jnl
A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling.
IEEE J. Solid State Circuits
Jason Howard, Saurabh Dighe, Sriram R. Vangal, Gregory Ruhl, Nitin Borkar, Shailendra Jain, Vasantha Erraguntla, Michael Konow, Michael Riepen, Matthias Gries, Guido Droege, Tor Lund-Larsen, Sebastian Steibl, Shekhar Borkar, Vivek K. De, Rob F. Van der Wijngaart
2011 J jnl
Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor.
IEEE J. Solid State Circuits
Saurabh Dighe, Sriram R. Vangal, Paolo A. Aseron, Shasi Kumar, Tiju Jacob, Keith A. Bowman, Jason Howard, James W. Tschanz, Vasantha Erraguntla, Nitin Borkar, Vivek K. De, Shekhar Borkar
2010 — conf
A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS.
ISSCC
Jason Howard, Saurabh Dighe, Yatin Vasant Hoskote, Sriram R. Vangal, David Finan, Gregory Ruhl, David Jenkins, Howard Wilson, Nitin Borkar, Gerhard Schrom, Fabric Pailet, Shailendra Jain, Tiju Jacob, Satish Yada, Sraven Marella, Praveen Salihundam, Vasantha Erraguntla, Michael Konow, Michael Riepen, Guido Droege, Joerg Lindemann, Matthias Gries, Thomas Apel, Kersten Henriss, Tor Lund-Larsen, Sebastian Steibl, Shekhar Borkar, Vivek De, Rob F. Van der Wijngaart, Timothy G. Mattson
2010 Misc conf
A 90mW/GFlop 3.4GHz Reconfigurable Fused/Continuous Multiply-Accumulator for Floating-Point and Integer Operands in 65nm.
VLSI Design
Shailendra Jain, Vasantha Erraguntla, Sriram R. Vangal, Yatin Vasant Hoskote, Nitin Borkar, Tulasi Mandepudi, V. P. Karthik
2010 A conf
The 48-core SCC Processor: the Programmer's View.
SC
Timothy G. Mattson, Michael Riepen, Thomas Lehnig, Paul Brett, Werner Haas, Patrick Kennedy, Jason Howard, Sriram R. Vangal, Nitin Borkar, Gregory Ruhl, Saurabh Dighe
2010 — conf
Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor.
ISSCC
Saurabh Dighe, Sriram R. Vangal, Paolo A. Aseron, Shasi Kumar, Tiju Jacob, Keith A. Bowman, Jason Howard, James W. Tschanz, Vasantha Erraguntla, Nitin Borkar, Vivek De, Shekhar Borkar
2009 J jnl
Process, Temperature, and Supply-Noise Tolerant 45nm Dense Cache Arrays With Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi-Vcc Circuits.
IEEE J. Solid State Circuits
Muhammad M. Khellah, Nam-Sung Kim, Yibin Ye, Dinesh Somasekhar, Tanay Karnik, Nitin Borkar, Gunjan Pandya, Fatih Hamzaoglu, Tom Coan, Yih Wang, Kevin Zhang, Clair Webb, Vivek De
2008 J jnl
An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS.
IEEE J. Solid State Circuits
Sriram R. Vangal, Jason Howard, Gregory Ruhl, Saurabh Dighe, Howard Wilson, James W. Tschanz, David Finan, Arvind P. Singh, Tiju Jacob, Shailendra Jain, Vasantha Erraguntla, Clark Roberts, Yatin Vasant Hoskote, Nitin Borkar, Shekhar Borkar
2007 J jnl
A 256-Kb Dual-V
IEEE J. Solid State Circuits
Muhammad M. Khellah, Dinesh Somasekhar, Yibin Ye, Nam-Sung Kim, Jason Howard, Gregory Ruhl, Murad Sunna, James W. Tschanz, Nitin Borkar, Fatih Hamzaoglu, Gunjan Pandya, Ali Farhang, Kevin Zhang, Vivek De
2007 J jnl
A 5-GHz Mesh Interconnect for a Teraflops Processor.
IEEE Micro
Yatin Hoskote, Sriram R. Vangal, Arvind P. Singh, Nitin Borkar, Shekhar Borkar
2007 — conf
Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging.
ISSCC
James W. Tschanz, Nam-Sung Kim, Saurabh Dighe, Jason Howard, Gregory Ruhl, Sriram R. Vangal, Siva G. Narendra, Yatin Hoskote, Howard Wilson, Carol Lam, Matthew Shuman, Carlos Tokunaga, Dinesh Somasekhar, Stephen Tang, David Finan, Tanay Karnik, Nitin Borkar, Nasser A. Kurd, Vivek De
2007 — conf
An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS.
ISSCC
Sriram R. Vangal, Jason Howard, Gregory Ruhl, Saurabh Dighe, Howard Wilson, James W. Tschanz, David Finan, Priya Iyer, Arvind P. Singh, Tiju Jacob, Shailendra Jain, Sriram Venkataraman, Yatin Hoskote, Nitin Borkar
2006 — conf
A 4.2GHz 0.3mm2 256kb Dual-V
ISSCC
Muhammad M. Khellah, Nam-Sung Kim, Jason Howard, Gregory Ruhl, Yibin Ye, James W. Tschanz, Dinesh Somasekhar, Nitin Borkar, Fatih Hamzaoglu, Gunjan Pandya, Ali Farhang, Kevin Zhang, Vivek De
2006 J jnl
A 6.2-GFlops Floating-Point Multiply-Accumulator With Conditional Normalization.
IEEE J. Solid State Circuits
Sriram R. Vangal, Yatin Vasant Hoskote, Nitin Borkar, Atila Alvandpour
2004 Misc conf
Design Challenges in Sub-100nm High Performance Microprocessors.
VLSI Design
Siva G. Narendra, Vasantha Erraguntla, James W. Tschanz, Nitin Borkar
2003 J jnl
A TCP offload accelerator for 10 Gb/s Ethernet in 90-nm CMOS.
IEEE J. Solid State Circuits
Yatin Vasant Hoskote, Bradley A. Bloechel, Gregory E. Dermer, Vasantha Erraguntla, David Finan, Jason Howard, Dan Klowden, Siva G. Narendra, Greg Ruhl, James W. Tschanz, Sriram R. Vangal, Venkat Veeramachaneni, Howard Wilson, Jianping Xu, Nitin Borkar
2002 J jnl
5-GHz 32-bit integer execution core in 130-nm dual-V
IEEE J. Solid State Circuits
Sriram R. Vangal, Mark A. Anders, Nitin Borkar, Erik Seligman, Venkatesh Govindarajulu, Vasantha Erraguntla, Howard Wilson, Amaresh Pangal, Venkat Veeramachaneni, James W. Tschanz, Yibin Ye, Dinesh Somasekhar, Bradley A. Bloechel, Gregory E. Dermer, Ram K. Krishnamurthy, Krishnamurthy Soumyanath, Sanu Mathew, Siva G. Narendra, Mircea R. Stan, Scott Thompson, Vivek De, Shekhar Borkar