Nithin Kumar Yernad Balachandra

13 papers Journal 9Unranked 4
YearRankTypeTitle / Venue / Authors
2024 J jnl
N-Parallel Paths-Based D-Latch for High-Speed Applications.
IEEE Access
Rakhi R., Siddharth R. K., K. G. Shreeharsha, M. H. Vasantha, Nithin Kumar Yernad Balachandra
2021 J jnl
Inexact Signed Wallace Tree Multiplier Design Using Reversible Logic.
IEEE Access
Sithara Raveendran, Pranose J. Edavoor, Nithin Kumar Yernad Balachandra, M. H. Vasantha
2020 J jnl
6.25 GHz, 1 mV input resolution auxiliary circuit assisted comparator in 65 nm CMOS process.
IET Circuits Devices Syst.
Siddharth Rajkumar Kala, Sushma Chandaka, Nithin Kumar Yernad Balachandra, Vasantha Moodabettu Harishchandra, Edoardo Bonizzoni
2020 J jnl
Design and implementation of image kernels using reversible logic gates.
IET Image Process.
Sithara Raveendran, Pranose J. Edavoor, Nithin Kumar Yernad Balachandra, Vasantha Moodabettu Harishchandra
2019 — conf
Process Corner Calibration for Standard Cell Based Flash ADC.
iSES
Pradeep R., Siddharth R. K., Nithin Kumar Yernad Balachandra, Vasantha Moodabettu Harishchandra
2019 — conf
Self Timed SRAM Array with Enhanced low Voltage Read and Write Capability.
ISVLSI
Prasad Vernekar, Nithin Kumar Yernad Balachandra, Vasantha Moodabettu Harishchandra
2019 — conf
Two-Step Flash ADC Using Standard Cell Based Flash ADCs.
iSES
Rahul E., Siddharth R. K., Vivek Sharma, M. H. Vasantha, Nithin Kumar Yernad Balachandra
2018 J jnl
An energy-efficient fault-aware core mapping in mesh-based network on chip systems.
J. Netw. Comput. Appl.
Naresh Kumar Reddy Beechu, Vasantha Moodabettu Harishchandra, Nithin Kumar Yernad Balachandra
2018 J jnl
Energy-Aware and Reliability-Aware Mapping for NoC-Based Architectures.
Wirel. Pers. Commun.
Naresh Kumar Reddy Beechu, Vasantha Moodabettu Harishchandra, Nithin Kumar Yernad Balachandra
2018 J jnl
Hardware implementation of fault tolerance NoC core mapping.
Telecommun. Syst.
Naresh Kumar Reddy Beechu, Vasantha Moodabettu Harishchandra, Nithin Kumar Yernad Balachandra
2017 — conf
High Performance Sense Amplifier Based Flip Flop for Driver Applications.
iNIS
Anoop D, Nithin Kumar Yernad Balachandra, Vasantha Moodabettu Harishchandra
2017 J jnl
High-performance and energy-efficient fault-tolerance core mapping in NoC.
Sustain. Comput. Informatics Syst.
Naresh Kumar Reddy Beechu, Vasantha Moodabettu Harishchandra, Nithin Kumar Yernad Balachandra
2017 J jnl
System level fault-tolerance core mapping and FPGA-based verification of NoC.
Microelectron. J.
Naresh Kumar Reddy Becchu, Vasantha Moodabettu Harishchandra, Nithin Kumar Yernad Balachandra