Nirmal R. Saxena

48 papers A* 1A 12B 2Misc 4Journal 21Unranked 8

Year	Rank	Type	Title / Venue / Authors
2025	A	`conf`	Invited Paper: Hardware-Software Co-Design for Highly Optimized, Customized, and Reliable AI Systems. ICCAD Jörg Henkel, Mehdi B. Tahoori, Heba Khdr, Hassan Nassar, Vincent Meyers, Deming Chen, Selin Yildirim, Yingbing Huang, Nirmal R. Saxena, Saurabh Hukerikar, Srivi Dhruvanarayan
2024	J	`jnl`	Optimal Checkpoint Interval with Availability as an Objective Function. CoRR Nirmal R. Saxena, Saurabh Hukerikar, Mikolaj Blaz, Swapna Raj
2024	—	`conf`	Optimizing Large-Scale Fault Injection Experiments through Martingale Hypothesis: A Systematic Approach for Reliability Assessment of Safety-Critical Systems. DSN-S Saurabh Hukerikar, Atieh Lotfi, Yanxiang Huang, Jason Campbell, Nirmal R. Saxena
2022	J	`jnl`	Characterizing and Mitigating Soft Errors in GPU DRAM. IEEE Micro Michael B. Sullivan, Nirmal R. Saxena, Mike O'Connor, Donghyuk Lee, Paul Racunas, Saurabh Hukerikar, Timothy Tsai, Siva Kumar Sastry Hari, Stephen W. Keckler
2022	A	`conf`	Error Model (EM) - A New Way of Doing Fault Simulation. ITC Nirmal R. Saxena, Atieh Lotfi
2022	A	`conf`	Runtime Fault Diagnostics for GPU Tensor Cores. ITC Saurabh Hukerikar, Nirmal R. Saxena
2021	A*	`conf`	Characterizing and Mitigating Soft Errors in GPU DRAM. MICRO Michael B. Sullivan, Nirmal R. Saxena, Mike O'Connor, Donghyuk Lee, Paul Racunas, Saurabh Hukerikar, Timothy Tsai, Siva Kumar Sastry Hari, Stephen W. Keckler
2020	A	`conf`	On the Measurement of Safe Fault Failure Rates in High-Performance Compute Processors. ITC Richard Bramley, Yanxiang Huang, Guangshan Duan, Nirmal R. Saxena, Paul Racunas
2019	A	`conf`	Resiliency of automotive object detection networks on GPU architectures. ITC Atieh Lotfi, Saurabh Hukerikar, Keshav Balasubramanian, Paul Racunas, Nirmal R. Saxena, Richard Bramley, Yanxiang Huang
2018	—	`conf`	Keynote 1: The road to resilient computing in autonomous driving is paved with redundancy. IRPS Nirmal R. Saxena, Sanu Mathew, Krishna Saraswat
2018	A	`conf`	Low Overhead Tag Error Mitigation for GPU Architectures. DSN Atieh Lotfi, Nirmal R. Saxena, Richard Bramley, Paul Racunas, Philip P. Shirvani
2008	Misc	`conf`	How Many Test Patterns are Useless? VTS François-Fabien Ferhani, Nirmal R. Saxena, Edward J. McCluskey, Phil Nigh
2004	J	`jnl`	Efficient Design Diversity Estimation for Combinational Circuits. IEEE Trans. Computers Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey
2004	J	`jnl`	Reconfigurable Architecture for Autonomous Self-Repair. IEEE Des. Test Comput. Subhasish Mitra, Wei-Je Huang, Nirmal R. Saxena, Shu-Yi Yu, Edward J. McCluskey
2002	J	`jnl`	A Design Diversity Metric and Analysis of Redundant Systems. IEEE Trans. Computers Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey
2001	A	`conf`	Techniques for Estimation of Design Diversity for Combinational Logic Circuits. DSN Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey
2000	Misc	`conf`	A Reliable LZ Data Compressor on Reconfigurable Coprocessors. FCCM Wei-Je Huang, Nirmal R. Saxena, Edward J. McCluskey
2000	Misc	`conf`	An ACS Robotic Control Algorithm with Fault Tolerant Capabilities. FCCM Shu-Yi Yu, Nirmal R. Saxena, Edward J. McCluskey
2000	J	`jnl`	Common-mode failures in redundant VLSI systems: a survey. IEEE Trans. Reliab. Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey
2000	J	`jnl`	Dependable Computing and Online Testing in Adaptive and Configurable Systems. IEEE Des. Test Comput. Nirmal R. Saxena, Santiago Fernández-Gomez, Wei-Je Huang, Subhasish Mitra, Shu-Yi Yu, Edward J. McCluskey
2000	Misc	`conf`	Fault Escapes in Duplex Systems. VTS Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey
2000	J	`jnl`	Software-implemented EDAC protection against SEUs. IEEE Trans. Reliab. Philip P. Shirvani, Nirmal R. Saxena, Edward J. McCluskey
1999	A	`conf`	A design diversity metric and reliability analysis for redundant systems. ITC Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey
1999	A	`conf`	Finite state machine synthesis with concurrent error detection. ITC Chaohuang Zeng, Nirmal R. Saxena, Edward J. McCluskey
1998	B	`conf`	Dependable adaptive computing systems-the ROAR project. SMC Nirmal R. Saxena, Edward J. McCluskey
1997	J	`jnl`	Parallel Signatur Analysis Design with Bounds on Aliasing. IEEE Trans. Computers Nirmal R. Saxena, Edward J. McCluskey
1996	J	`jnl`	Counting Two-State Transition-Tour Sequences. IEEE Trans. Computers Nirmal R. Saxena, Edward J. McCluskey
1996	A	`conf`	Generation of Test Cases for Hardware Design Verification of a Super-Scalar Fetch Processor. ITC Irith Pomeranz, Nirmal R. Saxena, Richard Reeve, Paritosh Kulkarni, Yan A. Li
1995	—	`conf`	Design Verification of a Super-Scalar RISC Processor. FTCS Babu Turumella, Aiman Kabakibo, Manjunath Bogadi, Karakunakara Menon, Shaleah Thusoo, Long Nguyen, Nirmal R. Saxena, Michael Chow
1995	—	`conf`	Error Detection and Handling in a Superscalar, Speculative Out-of-Order Execution Processor System. FTCS Nirmal R. Saxena, Chien Chen, Ravi Swami, Hideki Osone, Shalesh Thusoo, David Lyon, David Chang, Anand Dharmaraj, Niteen Patkar, Yizhi Lu, Ben Chia
1995	J	`jnl`	Fault-Tolerant Features in the HaL Memory Management Unit. IEEE Trans. Computers Nirmal R. Saxena, David Chih-Wei Chang, Kevin Dawallu, Jaspal Kohli, Pat Helland
1995	J	`jnl`	Floating Point Fault Tolerance with Backward Error Assertions. IEEE Trans. Computers Daniel Boley, Gene H. Golub, Samy Makar, Nirmal R. Saxena, Edward J. McCluskey
1995	B	`conf`	HALSIM - A Very Fast SPARC-V9 Behavioral Model. MASCOTS David R. Barach, Jaspal Kohli, John Slice, Marc Spaulding, Rajeev Bharadhwaj, Don Hudson, Cliff Neighbors, Nirmal R. Saxena, Rolland Crunk
1994	J	`jnl`	HALSIM - a very fast SPARC V9 behavioral model. SIGARCH Comput. Archit. News David R. Barach, Jaspal Kohli, John Slice, Marc Spaulding, Rajeev Bharadhwaj, Don Hudson, Cliff Neighbors, Nirmal R. Saxena, Rolland Crunk
1994	J	`jnl`	Linear Complexity Assertions for Sorting. IEEE Trans. Software Eng. Nirmal R. Saxena, Edward J. McCluskey
1993	—	`conf`	Algorithmic Synthesis of High Level Tests for Data Path Designs. FTCS Nirmal R. Saxena, Ravi Tangirala, Ajay Srivastava
1993	—	`conf`	Concurrent Error Detection/Correction in the HAL MMU Chip. FTCS David Chih-Wei Chang, Nirmal R. Saxena
1992	J	`jnl`	Simple Bounds on Serial Signature Analysis Aliasing for Random Testing. IEEE Trans. Computers Nirmal R. Saxena, Piero Franco, Edward J. McCluskey
1991	—	`conf`	Bounds on Signature Analysis Aliasing for Random Testing. FTCS Nirmal R. Saxena, Piero Franco, Edward J. McCluskey
1991	A	`conf`	Refined Bounds on Signature Analysis Aliasing for Random Testing. ITC Nirmal R. Saxena, Piero Franco, Edward J. McCluskey
1990	J	`jnl`	Analysis of Checksums, Extended-Precision Checksums, and Cyclic Redundancy Checks. IEEE Trans. Computers Nirmal R. Saxena, Edward J. McCluskey
1990	J	`jnl`	Control-Flow Checking Using Watchdog Assists and Extended-Precision Checksums. IEEE Trans. Computers Nirmal R. Saxena, Edward J. McCluskey
1989	A	`conf`	Arithmetic and galois checksums. ICCAD Nirmal R. Saxena, Edward J. McCluskey
1989	—	`conf`	Control-flow checking using watchdog assists and extended-precision checksums. FTCS Nirmal R. Saxena, Edward J. McCluskey
1988	J	`jnl`	Simultaneous signature and syndrome compression. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. John P. Robinson, Nirmal R. Saxena
1988	J	`jnl`	Syndrome and transition count are uncorrelated. IEEE Trans. Inf. Theory Nirmal R. Saxena, John P. Robinson
1987	J	`jnl`	A Unified View of Test Compression Methods. IEEE Trans. Computers John P. Robinson, Nirmal R. Saxena
1986	J	`jnl`	Accumulator Compression Testing. IEEE Trans. Computers Nirmal R. Saxena, John P. Robinson