Niranjan Kulkarni

18 papers A* 1A 1C 3Journal 8Unranked 5
YearRankTypeTitle / Venue / Authors
2026 J jnl
MAIDCS: Middleware with Artificial Intelligence for Device and Communication Security.
SN Comput. Sci.
Niranjan Kulkarni, Sanjay L. Nalbalwar, Anil B. Nandgaonkar, Brijesh Iyer
2023 J jnl
A New Approach to Clock Skewing for Area and Power Optimization of ASICs Using Differential Flipflops and Local Clocking.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ankit Wagle, Jinghua Yang, Niranjan Kulkarni, Sarma B. K. Vrudhula
2017 A* conf
A Clock Skewing Strategy to Reduce Power and Area of ASIC Circuits.
DAC
Niranjan Kulkarni, Aykut Dengi, Sarma B. K. Vrudhula
2016 J jnl
An Enhanced Edge Adaptive Steganography Approach Using Threshold Value for Region Selection.
CoRR
Sachin Mungmode, R. R. Sedamkar, Niranjan Kulkarni
2016 J jnl
Digital IP Protection Using Threshold Voltage Control.
CoRR
Joseph Davis, Niranjan Kulkarni, Jinghua Yang, Aykut Dengi, Sarma B. K. Vrudhula
2016 — conf
Digital IP protection using threshold voltage control.
ISQED
Joseph Davis, Niranjan Kulkarni, Jinghua Yang, Aykut Dengi, Sarma B. K. Vrudhula
2016 J jnl
Efficient Enumeration of Unidirectional Cuts for Technology Mapping of Boolean Networks.
CoRR
Niranjan Kulkarni, Sarma B. K. Vrudhula
2016 J jnl
Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops.
IEEE Trans. Very Large Scale Integr. Syst.
Niranjan Kulkarni, Jinghua Yang, Jae-sun Seo, Sarma B. K. Vrudhula
2015 C conf
Design of threshold logic gates using emerging devices.
ISCAS
Sarma B. K. Vrudhula, Niranjan Kulkarni, Jinghua Yang
2015 — conf
Dynamic and leakage power reduction of ASICs using configurable threshold logic gates.
CICC
Jinghua Yang, Joseph Davis, Niranjan Kulkarni, Jae-sun Seo, Sarma B. K. Vrudhula
2015 C conf
Fast and robust differential flipflops and their extension to multi-input threshold gates.
ISCAS
Jinghua Yang, Niranjan Kulkarni, Joseph Davis, Sarma B. K. Vrudhula
2014 — conf
A fast, energy efficient, field programmable threshold-logic array.
FPT
Niranjan Kulkarni, Jinghua Yang, Sarma B. K. Vrudhula
2014 — conf
Integration of threshold logic gates with RRAM devices for energy efficient and robust operation.
NANOARCH
Jinghua Yang, Niranjan Kulkarni, Shimeng Yu, Sarma B. K. Vrudhula
2014 J jnl
Spintronic Threshold Logic Array (STLA) - A compact, low leakage, non-volatile gate array architecture.
J. Parallel Distributed Comput.
Nishant Nukala, Niranjan Kulkarni, Sarma B. K. Vrudhula
2012 A conf
Minimizing area and power of sequential CMOS circuits using threshold decomposition.
ICCAD
Niranjan Kulkarni, Nishant Nukala, Sarma B. K. Vrudhula
2012 — conf
Spintronic threshold logic array (STLA) - a compact, low leakage, non-volatile gate array architecture.
NANOARCH
Nishant Nukala, Niranjan Kulkarni, Sarma B. K. Vrudhula
2011 J jnl
Identification of Threshold Functions and Synthesis of Threshold Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tejaswi Gowda, Sarma B. K. Vrudhula, Niranjan Kulkarni, Krzysztof S. Berezowski
2009 C conf
A Novel Approach to Cell Formation.
ICFCA
Radim Belohlávek, Niranjan Kulkarni, Vilém Vychodil