Niraj K. Jha - RankMe

514 papers A* 39A 51B 4C 34Misc 40Journal 298Unranked 46

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	An Alternative Trajectory for Generative AI. CoRR Margarita Belova, Yuval Kansal, Yihao Liang, Jiaxin Xiao, Niraj K. Jha
2026	J	`jnl`	CD4LM: Consistency Distillation and aDaptive Decoding for Diffusion Language Models. CoRR Yihao Liang, Ze Wang, Hao Chen, Ximeng Sun, Jialian Wu, Xiaodong Yu, Jiang Liu, Emad Barsoum, Zicheng Liu, Niraj K. Jha
2026	J	`jnl`	GraphMERT: Efficient and Scalable Distillation of Reliable Knowledge Graphs from Unstructured Data. Trans. Mach. Learn. Res. Margarita Belova, Jiaxin Xiao, Shikhar Tuli, Niraj K. Jha
2026	J	`jnl`	Knowledge Graphs are Implicit Reward Models: Path-Derived Signals Enable Compositional Reasoning. CoRR Yuval Kansal, Niraj K. Jha
2026	J	`jnl`	LinMU: Multimodal Understanding Made Linear. CoRR Hongjie Wang, Niraj K. Jha
2026	J	`jnl`	LinMU: Multimodal Understanding Made Linear. Trans. Mach. Learn. Res. Hongjie Wang, Niraj K. Jha
2025	J	`jnl`	Bottom-up Domain-specific Superintelligence: A Reliable Knowledge Graph is What We Need. CoRR Bhishma Dedhia, Yuval Kansal, Niraj K. Jha
2025	J	`jnl`	Energy-Efficient Domain-Specific Artificial Intelligence Models and Agents: Pathways and Paradigms. CoRR Abhijit Chatterjee, Niraj K. Jha, Jonathan D. Cohen, Thomas L. Griffiths, Hongjing Lu, Diana Marculescu, Ashiqur Rasul, Keshab K. Parhi
2025	J	`jnl`	Generating, Fast and Slow: Scalable Parallel Video Generation with Video Interface Networks. CoRR Bhishma Dedhia, David Bourgin, Krishna Kumar Singh, Yuheng Li, Yan Kang, Zhan Xu, Niraj K. Jha, Yuchen Liu
2025	J	`jnl`	GraphMERT: Efficient and Scalable Distillation of Reliable Knowledge Graphs from Unstructured Data. CoRR Margarita Belova, Jiaxin Xiao, Shikhar Tuli, Niraj K. Jha
2025	J	`jnl`	Learning Interpretable Differentiable Logic Networks for Tabular Regression. CoRR Chang Yue, Niraj K. Jha
2025	J	`jnl`	Learning Interpretable Differentiable Logic Networks for Time-Series Classification. CoRR Chang Yue, Niraj K. Jha
2025	A*	`conf`	LinGen: Towards High-Resolution Minute-Length Text-to-Video Generation with Linear Computational Complexity. CVPR Hongjie Wang, Chih-Yao Ma, Yen-Cheng Liu, Ji Hou, Tao Xu, Jialiang Wang, Felix Juefei-Xu, Yaqiao Luo, Peizhao Zhang, Tingbo Hou, Peter Vajda, Niraj K. Jha, Xiaoliang Dai
2025	J	`jnl`	Neural Slot Interpreters: Grounding Object Semantics in Emergent Slot Representations. Trans. Mach. Learn. Res. Bhishma Dedhia, Niraj K. Jha
2025	J	`jnl`	SweetDeep: A Wearable AI Solution for Real-Time Non-Invasive Diabetes Screening. CoRR Ian Henriques, Lynda Elhassar, Sarvesh Relekar, Denis Walrave, Shayan Hassantabar, Vishu Ghanakota, Adel Laoui, Mahmoud Aich, Rafia Tir, Mohamed Zerguine, Samir Louafi, Moncef Kimouche, Emmanuel Cosson, Niraj K. Jha
2024	A*	`conf`	Attention-Driven Training-Free Efficiency Enhancement of Diffusion Models. CVPR Hongjie Wang, Difan Liu, Yan Kang, Yijun Li, Zhe Lin, Niraj K. Jha, Yuchen Liu
2024	J	`jnl`	Attention-Driven Training-Free Efficiency Enhancement of Diffusion Models. CoRR Hongjie Wang, Difan Liu, Yan Kang, Yijun Li, Zhe Lin, Niraj K. Jha, Yuchen Liu
2024	J	`jnl`	COMFORT: A Continual Fine-Tuning Framework for Foundation Models Targeted at Consumer Healthcare. CoRR Chia-Hao Li, Niraj K. Jha
2024	J	`jnl`	CONFINE: Conformal Prediction for Interpretable Neural Networks. CoRR Linhui Huang, Sayeri Lala, Niraj K. Jha
2024	J	`jnl`	CTRL: Clustering Training Losses for Label Error Detection. IEEE Trans. Artif. Intell. Chang Yue, Niraj K. Jha
2024	J	`jnl`	DOCTOR: A Multi-Disease Detection Continual Learning Framework Based on Wearable Medical Sensors. ACM Trans. Embed. Comput. Syst. Chia-Hao Li, Niraj K. Jha
2024	—	`conf`	DynaMo: Accelerating Language Model Inference with Dynamic Multi-Token Sampling. NAACL-HLT Shikhar Tuli, Chi-Heng Lin, Yen-Chang Hsu, Niraj K. Jha, Yilin Shen, Hongxia Jin
2024	J	`jnl`	DynaMo: Accelerating Language Model Inference with Dynamic Multi-Token Sampling. CoRR Shikhar Tuli, Chi-Heng Lin, Yen-Chang Hsu, Niraj K. Jha, Yilin Shen, Hongxia Jin
2024	J	`jnl`	EdgeTran: Device-Aware Co-Search of Transformers for Efficient Inference on Mobile Edge Platforms. IEEE Trans. Mob. Comput. Shikhar Tuli, Niraj K. Jha
2024	J	`jnl`	Learning Interpretable Differentiable Logic Networks. CoRR Chang Yue, Niraj K. Jha
2024	J	`jnl`	Learning Interpretable Differentiable Logic Networks. IEEE Trans. Circuits Syst. Artif. Intell. Chang Yue, Niraj K. Jha
2024	J	`jnl`	LinGen: Towards High-Resolution Minute-Length Text-to-Video Generation with Linear Computational Complexity. CoRR Hongjie Wang, Chih-Yao Ma, Yen-Cheng Liu, Ji Hou, Tao Xu, Jialiang Wang, Felix Juefei-Xu, Yaqiao Luo, Peizhao Zhang, Tingbo Hou, Peter Vajda, Niraj K. Jha, Xiaoliang Dai
2024	J	`jnl`	METRIK: Measurement-Efficient Randomized Controlled Trials using Transformers with Input Masking. CoRR Sayeri Lala, Niraj K. Jha
2024	J	`jnl`	Neural Slot Interpreters: Grounding Object Semantics in Emergent Slot Representations. CoRR Bhishma Dedhia, Niraj K. Jha
2024	J	`jnl`	PAGE: Domain-Incremental Adaptation with Past-Agnostic Generative Replay for Smart Healthcare. CoRR Chia-Hao Li, Niraj K. Jha
2024	A*	`conf`	Zero-TPrune: Zero-Shot Token Pruning Through Leveraging of the Attention Graph in Pre-Trained Transformers. CVPR Hongjie Wang, Bhishma Dedhia, Niraj K. Jha
2023	—	`conf`	AIMED: AI-Mediated Exploration of Design: An Experience Report. CPS-IoT Week Workshops Sanjai Narain, Dana Chee, Pranav Iyer, Emily Mak, Ricardo Valdez, Manli Zhu, Niraj K. Jha, Jaime F. Fisac, Kai-Chieh Hsu, Prerit Terway, Kishore Pochiraju, Brendan J. Englot, Emil Pitz, Sean Rooney, Yewei Huang
2023	J	`jnl`	AccelTran: A Sparsity-Aware Accelerator for Dynamic Inference With Transformers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shikhar Tuli, Niraj K. Jha
2023	J	`jnl`	AccelTran: A Sparsity-Aware Accelerator for Dynamic Inference with Transformers. CoRR Shikhar Tuli, Niraj K. Jha
2023	J	`jnl`	BREATHE: Second-Order Gradients and Heteroscedastic Emulation based Design Space Exploration. CoRR Shikhar Tuli, Niraj K. Jha
2023	J	`jnl`	CODEBench: A Neural Architecture and Hardware Accelerator Co-Design Framework. ACM Trans. Embed. Comput. Syst. Shikhar Tuli, Chia-Hao Li, Ritvik Sharma, Niraj K. Jha
2023	J	`jnl`	DOCTOR: A Multi-Disease Detection Continual Learning Framework Based on Wearable Medical Sensors. CoRR Chia-Hao Li, Niraj K. Jha
2023	J	`jnl`	EdgeTran: Co-designing Transformers for Efficient Inference on Mobile Edge Platforms. CoRR Shikhar Tuli, Niraj K. Jha
2023	J	`jnl`	FlexiBERT: Are Current Transformer Architectures too Homogeneous and Rigid? J. Artif. Intell. Res. Shikhar Tuli, Bhishma Dedhia, Shreshth Tuli, Niraj K. Jha
2023	J	`jnl`	INFORM: Inverse Design Methodology for Constrained Multiobjective Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Prerit Terway, Niraj K. Jha
2023	A*	`conf`	Im-Promptu: In-Context Composition from Image Prompts. NeurIPS Bhishma Dedhia, Michael Chang, Jake Snell, Tom Griffiths, Niraj K. Jha
2023	J	`jnl`	Im-Promptu: In-Context Composition from Image Prompts. CoRR Bhishma Dedhia, Michael Chang, Jake C. Snell, Thomas L. Griffiths, Niraj K. Jha
2023	J	`jnl`	ML-FEED: Machine Learning Framework for Efficient Exploit Detection (Extended version). CoRR Tanujay Saha, Tamjid Al Rahat, Najwa Aaraj, Yuan Tian, Niraj K. Jha
2023	J	`jnl`	REPAIRS: Gaussian Mixture Model-based Completion and Optimization of Partially Specified Systems. ACM Trans. Embed. Comput. Syst. Prerit Terway, Niraj K. Jha
2023	J	`jnl`	SCouT: Synthetic Counterfactuals via Spatiotemporal Transformers for Actionable Healthcare. ACM Trans. Comput. Heal. Bhishma Dedhia, Roshini Balasubramanian, Niraj K. Jha
2023	J	`jnl`	SECRETS: Subject-Efficient Clinical Randomized Controlled Trials using Synthetic Intervention. CoRR Sayeri Lala, Niraj K. Jha
2023	—	`conf`	Smart Healthcare. ACM Great Lakes Symposium on VLSI Niraj K. Jha
2023	J	`jnl`	TUTOR: Training Neural Networks Using Decision Rules as Model Priors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shayan Hassantabar, Prerit Terway, Niraj K. Jha
2023	J	`jnl`	TransCODE: Co-Design of Transformers and Accelerators for Efficient Training and Inference. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shikhar Tuli, Niraj K. Jha
2023	J	`jnl`	TransCODE: Co-design of Transformers and Accelerators for Efficient Training and Inference. CoRR Shikhar Tuli, Niraj K. Jha
2023	J	`jnl`	Zero-TPrune: Zero-Shot Token Pruning through Leveraging of the Attention Graph in Pre-Trained Transformers. CoRR Hongjie Wang, Bhishma Dedhia, Niraj K. Jha
2022	J	`jnl`	CODEBench: A Neural Architecture and Hardware Accelerator Co-Design Framework. CoRR Shikhar Tuli, Chia-Hao Li, Ritvik Sharma, Niraj K. Jha
2022	J	`jnl`	CTRL: Clustering Training Losses for Label Error Detection. CoRR Chang Yue, Niraj K. Jha
2022	J	`jnl`	CURIOUS: Efficient Neural Architecture Search Based on a Performance Predictor and Evolutionary Search. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shayan Hassantabar, Xiaoliang Dai, Niraj K. Jha
2022	J	`jnl`	Convolutional Autoencoder-Based Transfer Learning for Multi-Task Image Inferences. IEEE Trans. Emerg. Top. Comput. Jie Lu, Naveen Verma, Niraj K. Jha
2022	J	`jnl`	Fast Design Space Exploration of Nonlinear Systems: Part I. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sanjai Narain, Emily Mak, Dana Chee, Brendan J. Englot, Kishore Pochiraju, Niraj K. Jha, Karthik S. Narayan
2022	J	`jnl`	Fast Design Space Exploration of Nonlinear Systems: Part II. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Prerit Terway, Kenza Hamidouche, Niraj K. Jha
2022	J	`jnl`	FlexiBERT: Are Current Transformer Architectures too Homogeneous and Rigid? CoRR Shikhar Tuli, Bhishma Dedhia, Shreshth Tuli, Niraj K. Jha
2022	J	`jnl`	Fully Dynamic Inference With Deep Neural Networks. IEEE Trans. Emerg. Top. Comput. Wenhan Xia, Hongxu Yin, Xiaoliang Dai, Niraj K. Jha
2022	J	`jnl`	GRAVITAS: Graphical Reticulated Attack Vectors for Internet-of-Things Aggregate Security. IEEE Trans. Emerg. Top. Comput. Jacob Brown, Tanujay Saha, Niraj K. Jha
2022	J	`jnl`	Incremental Learning Using a Grow-and-Prune Paradigm With Efficient Neural Networks. IEEE Trans. Emerg. Top. Comput. Xiaoliang Dai, Hongxu Yin, Niraj K. Jha
2022	J	`jnl`	MHDeep: Mental Health Disorder Detection System Based on Wearable Sensors and Artificial Neural Networks. ACM Trans. Embed. Comput. Syst. Shayan Hassantabar, Joe Zhang, Hongxu Yin, Niraj K. Jha
2022	—	`conf`	ML-FEED: Machine Learning Framework for Efficient Exploit Detection. TPS-ISA Tanujay Saha, Tamjid Al Rahat, Najwa Aaraj, Yuan Tian, Niraj K. Jha
2022	J	`jnl`	Machine Learning Assisted Security Analysis of 5G-Network-Connected Systems. IEEE Trans. Emerg. Top. Comput. Tanujay Saha, Najwa Aaraj, Niraj K. Jha
2022	J	`jnl`	SCANN: Synthesis of Compact and Accurate Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shayan Hassantabar, Zeyu Wang, Niraj K. Jha
2022	J	`jnl`	SCouT: Synthetic Counterfactuals via Spatiotemporal Transformers for Actionable Healthcare. CoRR Bhishma Dedhia, Roshini Balasubramanian, Niraj K. Jha
2022	J	`jnl`	SHARKS: Smart Hacking Approaches for RisK Scanning in Internet-of-Things and Cyber-Physical Systems Based on Machine Learning. IEEE Trans. Emerg. Top. Comput. Tanujay Saha, Najwa Aaraj, Neel Ajjarapu, Niraj K. Jha
2022	J	`jnl`	SPRING: A Sparsity-Aware Reduced-Precision Monolithic 3D CNN Accelerator Architecture for Training and Inference. IEEE Trans. Emerg. Top. Comput. Ye Yu, Niraj K. Jha
2022	J	`jnl`	Towards Execution-Efficient LSTMs via Hardware-Guided Grow-and-Prune Paradigm. IEEE Trans. Emerg. Top. Comput. Hongxu Yin, Guoyang Chen, Yingmin Li, Shuai Che, Weifeng Zhang, Niraj K. Jha
2021	J	`jnl`	CovidDeep: SARS-CoV-2/COVID-19 Test Based on Wearable Medical Sensors and Efficient Neural Networks. IEEE Trans. Consumer Electron. Shayan Hassantabar, Novati Stefano, Vishweshwar Ghanakota, Alessandra Ferrari, Gregory N. Nicola, Raffaele Bruno, Ignazio R. Marino, Kenza Hamidouche, Niraj K. Jha
2021	J	`jnl`	DiabDeep: Pervasive Diabetes Diagnosis Based on Wearable Medical Sensors and Efficient Neural Networks. IEEE Trans. Emerg. Top. Comput. Hongxu Yin, Bilal Mukadam, Xiaoliang Dai, Niraj K. Jha
2021	J	`jnl`	Fast Design Space Exploration of Nonlinear Systems: Part I. CoRR Sanjai Narain, Emily Mak, Dana Chee, Brendan J. Englot, Kishore Pochiraju, Niraj K. Jha, Karthik S. Narayan
2021	J	`jnl`	Fast Design Space Exploration of Nonlinear Systems: Part II. CoRR Prerit Terway, Kenza Hamidouche, Niraj K. Jha
2021	J	`jnl`	GRAVITAS: Graphical Reticulated Attack Vectors for Internet-of-Things Aggregate Security. CoRR Jacob Brown, Tanujay Saha, Niraj K. Jha
2021	J	`jnl`	HW/SW Framework for Improving the Safety of Implantable and Wearable Medical Devices. CoRR Malin Prematilake, Younghyun Kim, Vijay Raghunathan, Anand Raghunathan, Niraj K. Jha
2021	J	`jnl`	MHDeep: Mental Health Disorder Detection System based on Body-Area and Deep Neural Networks. CoRR Shayan Hassantabar, Joe Zhang, Hongxu Yin, Niraj K. Jha
2021	J	`jnl`	Machine Learning Assisted Security Analysis of 5G-Network-Connected Systems. CoRR Tanujay Saha, Najwa Aaraj, Niraj K. Jha
2021	J	`jnl`	SECRET: Semantically Enhanced Classification of Real-World Tasks. IEEE Trans. Computers Ayten Ozge Akmandor, Jorge Ortiz, Irene Manotas, Bongjun Ko, Niraj K. Jha
2021	J	`jnl`	SHARKS: Smart Hacking Approaches for RisK Scanning in Internet-of-Things and Cyber-Physical Systems based on Machine Learning. CoRR Tanujay Saha, Najwa Aaraj, Neel Ajjarapu, Niraj K. Jha
2021	J	`jnl`	Software-Defined Design Space Exploration for an Efficient DNN Accelerator Architecture. IEEE Trans. Computers Ye Yu, Yingmin Li, Shuai Che, Niraj K. Jha, Weifeng Zhang
2021	J	`jnl`	YSUY: Your Smartphone Understands You - Using Machine Learning to Address Fundamental Human Needs. IEEE Trans. Syst. Man Cybern. Syst. Ayten Ozge Akmandor, Xiaoliang Dai, Niraj K. Jha
2020	J	`jnl`	CovidDeep: SARS-CoV-2/COVID-19 Test Based on Wearable Medical Sensors and Efficient Neural Networks. CoRR Shayan Hassantabar, Novati Stefano, Vishweshwar Ghanakota, Alessandra Ferrari, Gregory N. Nicola, Raffaele Bruno, Ignazio R. Marino, Niraj K. Jha
2020	J	`jnl`	DISPATCH: Design Space Exploration of Cyber-Physical Systems. CoRR Prerit Terway, Kenza Hamidouche, Niraj K. Jha
2020	A*	`conf`	Dreaming to Distill: Data-Free Knowledge Transfer via DeepInversion. CVPR Hongxu Yin, Pavlo Molchanov, José M. Álvarez, Zhizhong Li, Arun Mallya, Derek Hoiem, Niraj K. Jha, Jan Kautz
2020	J	`jnl`	Efficient Synthesis of Compact Deep Neural Networks. CoRR Wenhan Xia, Hongxu Yin, Niraj K. Jha
2020	J	`jnl`	Fully Dynamic Inference with Deep Neural Networks. CoRR Wenhan Xia, Hongxu Yin, Xiaoliang Dai, Niraj K. Jha
2020	J	`jnl`	Grow and Prune Compact, Fast, and Accurate LSTMs. IEEE Trans. Computers Xiaoliang Dai, Hongxu Yin, Niraj K. Jha
2020	A*	`conf`	INVITED: Efficient Synthesis of Compact Deep Neural Networks. DAC Wenhan Xia, Hongxu Yin, Niraj K. Jha
2020	J	`jnl`	McPAT-Monolithic: An Area/Power/Timing Architecture Modeling Framework for 3-D Hybrid Monolithic Multicore Systems. IEEE Trans. Very Large Scale Integr. Syst. Abdullah Guler, Niraj K. Jha
2020	J	`jnl`	Robot Design With Neural Networks, MILP Solvers and Active Learning. CoRR Sanjai Narain, Emily Mak, Dana Chee, Todd Huster, Jeremy E. J. Cohen, Kishore Pochiraju, Brendan J. Englot, Niraj K. Jha, Karthik S. Narayan
2020	J	`jnl`	TUTOR: Training Neural Networks Using Decision Rules as Model Priors. CoRR Shayan Hassantabar, Prerit Terway, Niraj K. Jha
2019	A*	`conf`	ChamNet: Towards Efficient Network Design Through Platform-Aware Model Adaptation. CVPR Xiaoliang Dai, Peizhao Zhang, Bichen Wu, Hongxu Yin, Fei Sun, Yanghan Wang, Marat Dukhan, Yunqing Hu, Yiming Wu, Yangqing Jia, Peter Vajda, Matt Uyttendaele, Niraj K. Jha
2019	J	`jnl`	DiabDeep: Pervasive Diabetes Diagnosis based on Wearable Medical Sensors and Efficient Neural Networks. CoRR Hongxu Yin, Bilal Mukadam, Xiaoliang Dai, Niraj K. Jha
2019	J	`jnl`	Dreaming to Distill: Data-free Knowledge Transfer via DeepInversion. CoRR Hongxu Yin, Pavlo Molchanov, Zhizhong Li, José M. Álvarez, Arun Mallya, Derek Hoiem, Niraj K. Jha, Jan Kautz
2019	J	`jnl`	Hardware-Guided Symbiotic Training for Compact, Accurate, yet Execution-Efficient LSTM. CoRR Hongxu Yin, Guoyang Chen, Yingmin Li, Shuai Che, Weifeng Zhang, Niraj K. Jha
2019	J	`jnl`	Incremental Learning Using a Grow-and-Prune Paradigm with Efficient Neural Networks. CoRR Xiaoliang Dai, Hongxu Yin, Niraj K. Jha
2019	J	`jnl`	NeST: A Neural Network Synthesis Tool Based on a Grow-and-Prune Paradigm. IEEE Trans. Computers Xiaoliang Dai, Hongxu Yin, Niraj K. Jha
2019	J	`jnl`	SCANN: Synthesis of Compact and Accurate Neural Networks. CoRR Shayan Hassantabar, Zeyu Wang, Niraj K. Jha
2019	J	`jnl`	SECRET: Semantically Enhanced Classification of Real-world Tasks. CoRR Ayten Ozge Akmandor, Jorge Ortiz, Irene Manotas, Bongjun Ko, Niraj K. Jha
2019	J	`jnl`	SPRING: A Sparsity-Aware Reduced-Precision Monolithic 3D CNN Accelerator Architecture for Training and Inference. CoRR Ye Yu, Niraj K. Jha
2019	J	`jnl`	STEERAGE: Synthesis of Neural Networks Using Architecture Search and Grow-and-Prune Methods. CoRR Shayan Hassantabar, Xiaoliang Dai, Niraj K. Jha
2019	J	`jnl`	Software-Defined Design Space Exploration for an Efficient AI Accelerator Architecture. CoRR Ye Yu, Yingmin Li, Shuai Che, Niraj K. Jha, Weifeng Zhang
2019	J	`jnl`	Three-Dimensional Monolithic FinFET-Based 8T SRAM Cell Design for Enhanced Read Time and Low Leakage. IEEE Trans. Very Large Scale Integr. Syst. Abdullah Guler, Niraj K. Jha
2018	J	`jnl`	A Hierarchical Inference Model for Internet-of-Things. IEEE Trans. Multi Scale Comput. Syst. Hongxu Yin, Zeyu Wang, Niraj K. Jha
2018	J	`jnl`	A Monolithic 3D Hybrid Architecture for Energy-Efficient Computation. IEEE Trans. Multi Scale Comput. Syst. Ye Yu, Niraj K. Jha
2018	J	`jnl`	ChamNet: Towards Efficient Network Design through Platform-Aware Model Adaptation. CoRR Xiaoliang Dai, Peizhao Zhang, Bichen Wu, Hongxu Yin, Fei Sun, Yanghan Wang, Marat Dukhan, Yunqing Hu, Yiming Wu, Yangqing Jia, Peter Vajda, Matt Uyttendaele, Niraj K. Jha
2018	J	`jnl`	Detecting and Alleviating Stress with SoDA. Computer Ayten Ozge Akmandor, Niraj K. Jha
2018	J	`jnl`	Genetic Programming for Energy-Efficient and Energy-Scalable Approximate Feature Computation in Embedded Inference Systems. IEEE Trans. Computers Jie Lu, Hongyang Jia, Naveen Verma, Niraj K. Jha
2018	J	`jnl`	Grow and Prune Compact, Fast, and Accurate LSTMs. CoRR Xiaoliang Dai, Hongxu Yin, Niraj K. Jha
2018	J	`jnl`	Hybrid Monolithic 3-D IC Floorplanner. IEEE Trans. Very Large Scale Integr. Syst. Abdullah Guler, Niraj K. Jha
2018	C	`conf`	Keynotes. ICCE Linus Torvalds, Niraj K. Jha, Gary Davis, Nasir D. Memon, Petronel Bigioi, Swarup Bhunia, Koji Nakao
2018	J	`jnl`	OpSecure: A Secure Unidirectional Optical Channel for Implantable Medical Devices. IEEE Trans. Multi Scale Comput. Syst. Arsalan Mosenia, Niraj K. Jha
2018	J	`jnl`	PinMe: Tracking a Smartphone User around the World. CoRR Arsalan Mosenia, Xiaoliang Dai, Prateek Mittal, Niraj K. Jha
2018	J	`jnl`	PinMe: Tracking a Smartphone User around the World. IEEE Trans. Multi Scale Comput. Syst. Arsalan Mosenia, Xiaoliang Dai, Prateek Mittal, Niraj K. Jha
2018	—	`conf`	Simultaneously ensuring smartness, security, and energy efficiency in Internet-of-Things sensors. CICC Ayten Ozge Akmandor, Hongxu Yin, Niraj K. Jha
2018	J	`jnl`	Smart Health Care: An Edge-Side Computing Perspective. IEEE Consumer Electron. Mag. Ayten Ozge Akmandor, Niraj K. Jha
2018	J	`jnl`	Smart Healthcare. Found. Trends Electron. Des. Autom. Hongxu Yin, Ayten Ozge Akmandor, Arsalan Mosenia, Niraj K. Jha
2018	C	`conf`	Smart healthcare. ICCE Niraj K. Jha
2018	J	`jnl`	Smart, Secure, Yet Energy-Efficient, Internet-of-Things Sensors. IEEE Trans. Multi Scale Comput. Syst. Ayten Ozge Akmandor, Hongxu Yin, Niraj K. Jha
2018	J	`jnl`	Statistical Optimization of FinFET Processor Architectures under PVT Variations Using Dual Device-Type Assignment. ACM J. Emerg. Technol. Comput. Syst. Ye Yu, Niraj K. Jha
2017	J	`jnl`	A Comprehensive Study of Security of Internet-of-Things. IEEE Trans. Emerg. Top. Comput. Arsalan Mosenia, Niraj K. Jha
2017	J	`jnl`	A Health Decision Support System for Disease Diagnosis Based on Wearable Medical Sensors and Machine Learning Ensembles. IEEE Trans. Multi Scale Comput. Syst. Hongxu Yin, Niraj K. Jha
2017	J	`jnl`	Analytical Modeling of the SMART NoC. IEEE Trans. Multi Scale Comput. Syst. Debajit Bhattacharya, Niraj K. Jha
2017	J	`jnl`	Automated Quantum Circuit Synthesis and Cost Estimation for the Binary Welded Tree Oracle. ACM J. Emerg. Technol. Comput. Syst. Mrityunjay Ghosh, Amlan Chakrabarti, Niraj K. Jha
2017	J	`jnl`	CABA: Continuous Authentication Based on BioAura. IEEE Trans. Computers Arsalan Mosenia, Susmita Sur-Kolay, Anand Raghunathan, Niraj K. Jha
2017	J	`jnl`	DISASTER: Dedicated Intelligent Security Attacks on Sensor-Triggered Emergency Responses. IEEE Trans. Multi Scale Comput. Syst. Arsalan Mosenia, Susmita Sur-Kolay, Anand Raghunathan, Niraj K. Jha
2017	J	`jnl`	Improving Convergence and Simulation Time of Quantum Hydrodynamic Simulation: Application to Extraction of Best 10-nm FinFET Parameter Values. IEEE Trans. Very Large Scale Integr. Syst. Xiaoliang Dai, Niraj K. Jha
2017	—	`conf`	Internet-of-Medical-Things. ACM Great Lakes Symposium on VLSI Niraj K. Jha
2017	J	`jnl`	Keep the Stress Away with SoDA: Stress Detection and Alleviation System. IEEE Trans. Multi Scale Comput. Syst. Ayten Ozge Akmandor, Niraj K. Jha
2017	J	`jnl`	NeST: A Neural Network Synthesis Tool Based on a Grow-and-Prune Paradigm. CoRR Xiaoliang Dai, Hongxu Yin, Niraj K. Jha
2017	J	`jnl`	Using a Device State Library to Boost the Performance of TCAD Mixed-Mode Simulation. IEEE Trans. Very Large Scale Integr. Syst. Xiaoliang Dai, Niraj K. Jha
2017	J	`jnl`	Wearable Medical Sensor-Based System Design: A Survey. IEEE Trans. Multi Scale Comput. Syst. Arsalan Mosenia, Susmita Sur-Kolay, Anand Raghunathan, Niraj K. Jha
2016	J	`jnl`	A 3-D CPU-FPGA-DRAM Hybrid Architecture for Low-Power Computation. IEEE Trans. Very Large Scale Integr. Syst. Xianmin Chen, Niraj K. Jha
2016	J	`jnl`	Compressed Signal Processing on Nyquist-Sampled Signals. IEEE Trans. Computers Jie Lu, Naveen Verma, Niraj K. Jha
2016	J	`jnl`	Delay/Power Modeling and Optimization of FinFET Circuit Modules under PVT Variations: Observing the Trends between the 22nm and 14nm Technology Nodes. ACM J. Emerg. Technol. Comput. Syst. Aoxiang Tang, Xun Gao, Lung-Yen Chen, Niraj K. Jha
2016	Misc	`conf`	Fast FinFET Device Simulation under Process-Voltage Variations Using an Assisted Speed-Up Mechanism. VLSID Sourindra Chaudhuri, Ajay N. Bhoj, Debajit Bhattacharya, Niraj K. Jha
2016	J	`jnl`	GenFin: Genetic Algorithm-Based Multiobjective Statistical Logic Circuit Optimization Using Incremental Statistical Analysis. IEEE Trans. Very Large Scale Integr. Syst. Aoxiang Tang, Niraj K. Jha
2016	J	`jnl`	Physiological Information Leakage: A New Frontier in Health Information Security. IEEE Trans. Emerg. Top. Comput. Arsalan Mohsen Nia, Susmita Sur-Kolay, Anand Raghunathan, Niraj K. Jha
2016	J	`jnl`	Reducing Wire and Energy Overheads of the SMART NoC Using a Setup Request Network. IEEE Trans. Very Large Scale Integr. Syst. Xianmin Chen, Niraj K. Jha
2016	J	`jnl`	TCAD-Assisted Capacitance Extraction of FinFET SRAM and Logic Arrays. IEEE Trans. Very Large Scale Integr. Syst. Debajit Bhattacharya, Niraj K. Jha
2016	J	`jnl`	Ultra-High Density Monolithic 3-D FinFET SRAM With Enhanced Read Stability. IEEE Trans. Circuits Syst. I Regul. Pap. Debajit Bhattacharya, Niraj K. Jha
2016	J	`jnl`	Ultra-Low-Leakage and High-Performance Logic Circuit Design Using Multiparameter Asymmetric FinFETs. ACM J. Emerg. Technol. Comput. Syst. Sourindra M. Chaudhuri, Niraj K. Jha
2016	J	`jnl`	Ultra-low-leakage, Robust FinFET SRAM Design Using Multiparameter Asymmetric FinFETs. ACM J. Emerg. Technol. Comput. Syst. Abdullah Guler, Niraj K. Jha
2015	J	`jnl`	Design of Efficient Content Addressable Memories in High-Performance FinFET Technology. IEEE Trans. Very Large Scale Integr. Syst. Debajit Bhattacharya, Ajay N. Bhoj, Niraj K. Jha
2015	J	`jnl`	Energy-Efficient Long-term Continuous Personal Health Monitoring. IEEE Trans. Multi Scale Comput. Syst. Arsalan Mohsen Nia, Mehran Mozaffari Kermani, Susmita Sur-Kolay, Anand Raghunathan, Niraj K. Jha
2015	J	`jnl`	FDR 2.0: A Low-Power Dynamically Reconfigurable Architecture and Its FinFET Implementation. IEEE Trans. Very Large Scale Integr. Syst. Ting-Jung Lin, Wei Zhang, Niraj K. Jha
2015	J	`jnl`	McPAT-PVT: Delay and Power Modeling Framework for FinFET Processor Architectures Under PVT Variations. IEEE Trans. Very Large Scale Integr. Syst. Aoxiang Tang, Yang Yang, Chun-Yi Lee, Niraj K. Jha
2015	J	`jnl`	PAQCS: Physical Design-Aware Fault-Tolerant Quantum Circuit Synthesis. IEEE Trans. Very Large Scale Integr. Syst. Chia-Chun Lin, Susmita Sur-Kolay, Niraj K. Jha
2015	J	`jnl`	Signal Processing With Direct Computations on Compressively Sensed Data. IEEE Trans. Very Large Scale Integr. Syst. Mohammed Shoaib, Niraj K. Jha, Naveen Verma
2015	C	`conf`	Synthesis of Quantum Circuits for Dedicated Physical Machine Descriptions. RC Philipp Niemann, Saikat Basu, Amlan Chakrabarti, Niraj K. Jha, Robert Wille
2015	J	`jnl`	Systematic Poisoning Attacks on and Defenses for Machine Learning in Healthcare. IEEE J. Biomed. Health Informatics Mehran Mozaffari Kermani, Susmita Sur-Kolay, Anand Raghunathan, Niraj K. Jha
2015	A*	`conf`	Vibration-based secure side channel for medical devices. DAC Younghyun Kim, Woo Suk Lee, Vijay Raghunathan, Niraj K. Jha, Anand Raghunathan
2015	J	`jnl`	gem5-PVT: A Framework for FinFET System Simulation under PVT Variations. ACM J. Emerg. Technol. Comput. Syst. Xianmin Chen, Niraj K. Jha
2014	J	`jnl`	3D vs. 2D Device Simulation of FinFET Logic Gates under PVT Variations. ACM J. Emerg. Technol. Comput. Syst. Sourindra Chaudhuri, Niraj K. Jha
2014	J	`jnl`	A 0.6-107 µW Energy-Scalable Processor for Directly Analyzing Compressively-Sensed EEG. IEEE Trans. Circuits Syst. I Regul. Pap. Mohammed Shoaib, Kyong-Ho Lee, Niraj K. Jha, Naveen Verma
2014	J	`jnl`	A Fine-Grain Dynamically Reconfigurable Architecture Aimed at Reducing the FPGA-ASIC Gaps. IEEE Trans. Very Large Scale Integr. Syst. Ting-Jung Lin, Wei Zhang, Niraj K. Jha
2014	J	`jnl`	A defense framework against malware and vulnerability exploits. Int. J. Inf. Sec. Meng Zhang, Anand Raghunathan, Niraj K. Jha
2014	J	`jnl`	Accurate Leakage/Delay Estimation for FinFET Standard Cells under PVT Variations using the Response Surface Methodology. ACM J. Emerg. Technol. Comput. Syst. Sourindra M. Chaudhuri, Prateek Mishra, Niraj K. Jha
2014	J	`jnl`	FTQLS: Fault-Tolerant Quantum Logic Synthesis. IEEE Trans. Very Large Scale Integr. Syst. Chia-Chun Lin, Amlan Chakrabarti, Niraj K. Jha
2014	J	`jnl`	FinCANON: A PVT-Aware Integrated Delay and Power Modeling Framework for FinFET-Based Caches and On-Chip Networks. IEEE Trans. Very Large Scale Integr. Syst. Chun-Yi Lee, Niraj K. Jha
2014	Misc	`conf`	FinFET Logic Circuit Optimization with Different FinFET Styles: Lower Power Possible at Higher Supply Voltage. VLSID Sourindra Chaudhuri, Niraj K. Jha
2014	J	`jnl`	FinPrin: FinFET Logic Circuit Analysis and Optimization Under PVT Variations. IEEE Trans. Very Large Scale Integr. Syst. Yang Yang, Niraj K. Jha
2014	J	`jnl`	Parasitics-Aware Design of Symmetric and Asymmetric Gate-Workfunction FinFET SRAMs. IEEE Trans. Very Large Scale Integr. Syst. Ajay N. Bhoj, Niraj K. Jha
2014	J	`jnl`	QLib: Quantum module library. ACM J. Emerg. Technol. Comput. Syst. Chia-Chun Lin, Amlan Chakrabarti, Niraj K. Jha
2014	J	`jnl`	RMDDS: Reed-muller decision diagram synthesis of reversible logic circuits. ACM J. Emerg. Technol. Comput. Syst. Chia-Chun Lin, Niraj K. Jha
2014	—	`conf`	TCAD structure synthesis and capacitance extraction of a voltage-controlled oscillator using automated layout-to-device synthesis methodology. CICC Debajit Bhattacharya, Rajiv V. Joshi, Herschel A. Ainspan, Ninad D. Sathaye, Mohit Bajaj, Suresh Gundapaneni, Niraj K. Jha
2014	J	`jnl`	Trustworthiness of Medical Devices and Body Area Networks. Proc. IEEE Meng Zhang, Anand Raghunathan, Niraj K. Jha
2014	J	`jnl`	Ultra-low-leakage chip multiprocessor design with hybrid FinFET logic styles. ACM J. Emerg. Technol. Comput. Syst. Xianmin Chen, Niraj K. Jha
2013	J	`jnl`	3-D-TCAD-Based Parasitic Capacitance Extraction for Emerging Multigate Devices and Circuits. IEEE Trans. Very Large Scale Integr. Syst. Ajay N. Bhoj, Rajiv V. Joshi, Niraj K. Jha
2013	J	`jnl`	Algorithm-Driven Architectural Design Space Exploration of Domain-Specific Medical-Sensor Processors. IEEE Trans. Very Large Scale Integr. Syst. Mohammed Shoaib, Niraj K. Jha, Naveen Verma
2013	J	`jnl`	Design of Logic Gates and Flip-Flops in High-Performance FinFET Technology. IEEE Trans. Very Large Scale Integr. Syst. Ajay N. Bhoj, Niraj K. Jha
2013	J	`jnl`	Design space exploration of FinFET cache. ACM J. Emerg. Technol. Comput. Syst. Aoxiang Tang, Niraj K. Jha
2013	J	`jnl`	Efficient Methodologies for 3-D TCAD Modeling of Emerging Devices and Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ajay N. Bhoj, Rajiv V. Joshi, Niraj K. Jha
2013	Misc	`conf`	Embedded Reconfigurable Augmented DC-DC Boost Converter for Fast Transient Recovery. VLSI Design Neeraj Mishra, Niraj K. Jha, Santanu Kapat, Amit Patra
2013	Misc	`conf`	Emerging Frontiers in Embedded Security. VLSI Design Mehran Mozaffari Kermani, Meng Zhang, Anand Raghunathan, Niraj K. Jha
2013	Misc	`conf`	Energy-efficient and Secure Sensor Data Transmission Using Encompression. VLSI Design Meng Zhang, Mehran Mozaffari Kermani, Anand Raghunathan, Niraj K. Jha
2013	Misc	`conf`	Fin Prin: Analysis and Optimization of FinFET Logic Circuits under PVT Variations. VLSI Design Yang Yang, Niraj K. Jha
2013	J	`jnl`	Improving the Trustworthiness of Medical Device Software with Formal Verification Methods. IEEE Embed. Syst. Lett. Chunxiao Li, Anand Raghunathan, Niraj K. Jha
2013	Misc	`conf`	Localized Heating for Building Energy Efficiency. VLSI Design Jun Wei Chuah, Chunxiao Li, Niraj K. Jha, Anand Raghunathan
2013	J	`jnl`	MedMon: Securing Medical Devices Through Wireless Monitoring and Anomaly Detection. IEEE Trans. Biomed. Circuits Syst. Meng Zhang, Anand Raghunathan, Niraj K. Jha
2013	J	`jnl`	Optimized Quantum Gate Library for Various Physical Machine Descriptions. IEEE Trans. Very Large Scale Integr. Syst. Chia-Chun Lin, Amlan Chakrabarti, Niraj K. Jha
2013	J	`jnl`	Thermal Characterization of Test Techniques for FinFET and 3D Integrated Circuits. ACM J. Emerg. Technol. Comput. Syst. Aoxiang Tang, Niraj K. Jha
2013	A*	`conf`	Towards trustworthy medical devices and body area networks. DAC Meng Zhang, Anand Raghunathan, Niraj K. Jha
2013	J	`jnl`	Variable-Pipeline-Stage Router. IEEE Trans. Very Large Scale Integr. Syst. Chun-Yi Lee, Niraj K. Jha
2012	J	`jnl`	A Trusted Virtual Machine in an Untrusted Management Environment. IEEE Trans. Serv. Comput. Chunxiao Li, Anand Raghunathan, Niraj K. Jha
2012	—	`conf`	A compressed-domain processor for seizure detection to simultaneously reduce computation and communication energy. CICC Mohammed Shoaib, Niraj K. Jha, Naveen Verma
2012	Misc	`conf`	Accurate Leakage Estimation for FinFET Standard Cells Using the Response Surface Methodology. VLSI Design Sourindra Chaudhuri, Prateek Mishra, Niraj K. Jha
2012	—	`conf`	Design of Quantum Circuits for Random Walk Algorithms. ISVLSI Amlan Chakrabarti, Chia-Chun Lin, Niraj K. Jha
2012	A	`conf`	Enabling advanced inference on sensor nodes through direct use of compressively-sensed signals. DATE Mohammed Shoaib, Niraj K. Jha, Naveen Verma
2012	J	`jnl`	INVISIOS: A Lightweight, Minimally Intrusive Secure Execution Environment. ACM Trans. Embed. Comput. Syst. Divya Arora, Najwa Aaraj, Anand Raghunathan, Niraj K. Jha
2012	J	`jnl`	SRAM-Based NATURE: A Dynamically Reconfigurable FPGA Based on 10T Low-Power SRAMs. IEEE Trans. Very Large Scale Integr. Syst. Ting-Jung Lin, Wei Zhang, Niraj K. Jha
2012	J	`jnl`	Secure reconfiguration of software-defined radio. ACM Trans. Embed. Comput. Syst. Chunxiao Li, Niraj K. Jha, Anand Raghunathan
2011	C	`conf`	3D vs. 2D analysis of FinFET logic gates under process variations. ICCD Sourindra Chaudhuri, Niraj K. Jha
2011	J	`jnl`	A framework for defending embedded systems against software attacks. ACM Trans. Embed. Comput. Syst. Najwa Aaraj, Anand Raghunathan, Niraj K. Jha
2011	A*	`conf`	A low-energy computation platform for data-driven biomedical monitoring algorithms. DAC Mohammed Shoaib, Niraj K. Jha, Naveen Verma
2011	A*	`conf`	CACTI-FinFET: an integrated delay and power modeling framework for FinFET-based caches under process variations. DAC Chun-Yi Lee, Niraj K. Jha
2011	—	`conf`	Design of ultra-low-leakage logic gates and flip-flops in high-performance FinFET technology. ISQED Ajay N. Bhoj, Niraj K. Jha
2011	J	`jnl`	Editorial Announcing a New Editor-in-Chief. IEEE Trans. Very Large Scale Integr. Syst. Niraj K. Jha
2011	J	`jnl`	FinFET-Based Power Management for Improved DPA Resistance with Low Overhead. ACM J. Emerg. Technol. Comput. Syst. Meng Zhang, Niraj K. Jha
2010	C	`conf`	A Secure User Interface for Web Applications Running Under an Untrusted Operating System. CIT Chunxiao Li, Anand Raghunathan, Niraj K. Jha
2010	—	`conf`	Die-level leakage power analysis of FinFET circuits considering process variations. ISQED Prateek Mishra, Ajay N. Bhoj, Niraj K. Jha
2010	J	`jnl`	Editorial: New Associate Editor Appointments. IEEE Trans. Very Large Scale Integr. Syst. Niraj K. Jha
2010	—	`conf`	Fault modeling for FinFET circuits. NANOARCH Muzaffer O. Simsir, Ajay N. Bhoj, Niraj K. Jha
2010	J	`jnl`	FinFET-based power simulator for interconnection networks. ACM J. Emerg. Technol. Comput. Syst. Chun-Yi Lee, Niraj K. Jha
2010	J	`jnl`	Gated-diode FinFET DRAMs: Device and circuit design-considerations. ACM J. Emerg. Technol. Comput. Syst. Ajay N. Bhoj, Niraj K. Jha
2010	J	`jnl`	Low-power 3D nano/CMOS hybrid dynamically reconfigurable architecture. ACM J. Emerg. Technol. Comput. Syst. Wei Zhang, Niraj K. Jha, Li Shang
2010	A	`conf`	Low-power FinFET circuit synthesis using surface orientation optimization. DATE Prateek Mishra, Niraj K. Jha
2010	—	`conf`	NanoV: Nanowire-based VLSI design. NANOARCH Muzaffer O. Simsir, Niraj K. Jha
2010	—	`conf`	Secure Virtual Machine Execution under an Untrusted Management OS. IEEE CLOUD Chunxiao Li, Anand Raghunathan, Niraj K. Jha
2009	J	`jnl`	A hybrid Nano/CMOS dynamically reconfigurable system - Part II: Design optimization flow. ACM J. Emerg. Technol. Comput. Syst. Wei Zhang, Niraj K. Jha, Li Shang
2009	J	`jnl`	A hybrid nano-CMOS architecture for defect and fault tolerance. ACM J. Emerg. Technol. Comput. Syst. Muzaffer O. Simsir, Srihari Cadambi, Franjo Ivancic, Martin Rötteler, Niraj K. Jha
2009	J	`jnl`	A hybrid nano/CMOS dynamically reconfigurable system - Part I: Architecture. ACM J. Emerg. Technol. Comput. Syst. Wei Zhang, Niraj K. Jha, Li Shang
2009	A	`conf`	An architecture for secure software defined radio. DATE Chunxiao Li, Anand Raghunathan, Niraj K. Jha
2009	J	`jnl`	Design space exploration and data memory architecture design for a hybrid nano/CMOS dynamically reconfigurable architecture. ACM J. Emerg. Technol. Comput. Syst. Wei Zhang, Niraj K. Jha, Li Shang
2009	J	`jnl`	Editorial Appointments for the 2009-2010 Term. IEEE Trans. Very Large Scale Integr. Syst. Niraj K. Jha
2009	J	`jnl`	Fast Enhancement of Validation Test Sets for Improving the Stuck-at Fault Coverage of RTL Circuits. IEEE Trans. Very Large Scale Integr. Syst. Loganathan Lingappan, Vijay Gangaram, Niraj K. Jha, Sreejit Chakravarty
2009	C	`conf`	FinFET-based dynamic power management of on-chip interconnection networks through adaptive back-gate biasing. ICCD Chun-Yi Lee, Niraj K. Jha
2009	B	`conf`	GARNET: A detailed on-chip network model inside a full-system simulator. ISPASS Niket Agarwal, Tushar Krishna, Li-Shiuan Peh, Niraj K. Jha
2009	A*	`conf`	In-Network Snoop Ordering (INSO): Snoopy coherence on unordered interconnects. HPCA Niket Agarwal, Li-Shiuan Peh, Niraj K. Jha
2009	A*	`conf`	In-network coherence filtering: snoopy coherence without broadcasts. MICRO Niket Agarwal, Li-Shiuan Peh, Niraj K. Jha
2009	J	`jnl`	Low-power FinFET circuit synthesis using multiple supply and threshold voltages. ACM J. Emerg. Technol. Comput. Syst. Prateek Mishra, Anish Muttreja, Niraj K. Jha
2009	C	`conf`	Pragmatic design of gated-diode FinFET DRAMs. ICCD Ajay N. Bhoj, Niraj K. Jha
2009	A	`conf`	Thermal characterization of BIST, scan design and sequential test methodologies. ITC Muzaffer O. Simsir, Niraj K. Jha
2008	A	`conf`	A system-level perspective for efficient NoC design. IPDPS Amit Kumar, Niket Agarwal, Li-Shiuan Peh, Niraj K. Jha
2008	J	`jnl`	An energy-aware framework for dynamic software management in mobile computing systems. ACM Trans. Embed. Comput. Syst. Yunsi Fei, Lin Zhong, Niraj K. Jha
2008	J	`jnl`	Analysis and design of a hardware/software trusted platform module for embedded systems. ACM Trans. Embed. Comput. Syst. Najwa Aaraj, Anand Raghunathan, Niraj K. Jha
2008	J	`jnl`	Automatic Test Generation for Combinational Threshold Logic Networks. IEEE Trans. Very Large Scale Integr. Syst. Pallav Gupta, Rui Zhang, Niraj K. Jha
2008	B	`conf`	Dynamic Binary Instrumentation-Based Framework for Malware Defense. DIMVA Najwa Aaraj, Anand Raghunathan, Niraj K. Jha
2008	—	`conf`	Evaluation of multiple supply and threshold voltages for low-power FinFET circuit synthesis. NANOARCH Prateek Mishra, Anish Muttreja, Niraj K. Jha
2008	Misc	`conf`	Fault-Tolerant Computing Using a Hybrid Nano-CMOS Architecture. VLSI Design Muzaffer O. Simsir, Srihari Cadambi, Franjo Ivancic, Martin Rötteler, Niraj K. Jha
2008	J	`jnl`	Reversible logic synthesis with Fredkin and Peres gates. ACM J. Emerg. Technol. Comput. Syst. James Donald, Niraj K. Jha
2008	J	`jnl`	System-Level Dynamic Thermal Management for High-Performance Microprocessors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Amit Kumar, Li Shang, Li-Shiuan Peh, Niraj K. Jha
2008	Misc	`conf`	Threshold Voltage Control through Multiple Supply Voltages for Power-Efficient FinFET Interconnects. VLSI Design Anish Muttreja, Prateek Mishra, Niraj K. Jha
2008	A*	`conf`	Token flow control. MICRO Amit Kumar, Li-Shiuan Peh, Niraj K. Jha
2008	J	`jnl`	Toward Ideal On-Chip Communication Using Express Virtual Channels. IEEE Micro Amit Kumar, Li-Shiuan Peh, Partha Kundu, Niraj K. Jha
2008	Misc	`conf`	Variability-Tolerant Register-Transfer Level Synthesis. VLSI Design Anish Muttreja, Srivaths Ravi, Niraj K. Jha
2007	C	`conf`	A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS. ICCD Amit Kumar, Partha Kundu, Arvind P. Singh, Li-Shiuan Peh, Niraj K. Jha
2007	J	`jnl`	A Synthesis Methodology for Hybrid Custom Instruction and Coprocessor Generation for Extensible Processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2007	J	`jnl`	A Test Generation Framework for Quantum Cellular Automata Circuits. IEEE Trans. Very Large Scale Integr. Syst. Pallav Gupta, Niraj K. Jha, Loganathan Lingappan
2007	J	`jnl`	Aiding Side-Channel Attacks on Cryptographic Software With Satisfiability-Based Analysis. IEEE Trans. Very Large Scale Integr. Syst. Nachiketh R. Potlapally, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha, Ruby B. Lee
2007	J	`jnl`	Architectural Support for Run-Time Validation of Program Data Properties. IEEE Trans. Very Large Scale Integr. Syst. Divya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2007	J	`jnl`	Automated Energy/Performance Macromodeling of Embedded Software. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
2007	C	`conf`	CMOS logic design with independent-gate FinFETs. ICCD Anish Muttreja, Niket Agarwal, Niraj K. Jha
2007	J	`jnl`	Configuration and Extension of Embedded Processors to Optimize IPSec Protocol Execution. IEEE Trans. Very Large Scale Integr. Syst. Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Ruby B. Lee, Niraj K. Jha
2007	J	`jnl`	Editorial. IEEE Trans. Very Large Scale Integr. Syst. Niraj K. Jha
2007	J	`jnl`	Efficient Design for Testability Solution Based on Unsatisfiability for Register-Transfer Level Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Loganathan Lingappan, Niraj K. Jha
2007	A	`conf`	Energy and execution time analysis of a software-based trusted platform module. DATE Najwa Aaraj, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
2007	—	`conf`	Energy comparison and optimization of wireless body-area network technologies. BODYNETS Le Yan, Lin Zhong, Niraj K. Jha
2007	J	`jnl`	Energy-optimizing source code transformations for operating system-driven embedded software. ACM Trans. Embed. Comput. Syst. Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2007	J	`jnl`	Exploring Software Partitions for Fast Security Processing on a Multiprocessor Mobile SoC. IEEE Trans. Very Large Scale Integr. Syst. Divya Arora, Anand Raghunathan, Srivaths Ravi, Murugan Sankaradass, Niraj K. Jha, Srimat T. Chakradhar
2007	A*	`conf`	Express virtual channels: towards the ideal interconnection fabric. ISCA Amit Kumar, Li-Shiuan Peh, Partha Kundu, Niraj K. Jha
2007	Misc	`conf`	Fast Enhancement of Validation Test Sets to Improve Stuck-at Fault Coverage for RTL circuits. VLSI Design Loganathan Lingappan, Vijay Gangaram, Niraj K. Jha
2007	J	`jnl`	Generation of Heterogeneous Distributed Architectures for Memory-Intensive Applications Through High-Level Synthesis. IEEE Trans. Very Large Scale Integr. Syst. Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2007	J	`jnl`	Hybrid Architectures for Efficient and Secure Face Authentication in Embedded Systems. IEEE Trans. Very Large Scale Integr. Syst. Najwa Aaraj, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2007	J	`jnl`	Hybrid Simulation for Energy Estimation of Embedded Software. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
2007	J	`jnl`	Majority and Minority Network Synthesis With Application to QCA-, SET-, and TPL-Based Nanotechnologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Rui Zhang, Pallav Gupta, Niraj K. Jha
2007	A*	`conf`	NanoMap: An Integrated Design Optimization Flow for a Hybrid Nanotube/CMOS Dynamically Reconfigurable Architecture. DAC Wei Zhang, Li Shang, Niraj K. Jha
2007	J	`jnl`	Power-Efficient Scheduling for Heterogeneous Distributed Real-Time Embedded Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jiong Luo, Niraj K. Jha
2007	J	`jnl`	SLOPES: Hardware-Software Cosynthesis of Low-Power Real-Time Distributed Embedded Systems With Dynamically Reconfigurable FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Li Shang, Robert P. Dick, Niraj K. Jha
2007	J	`jnl`	Satisfiability-Based Automatic Test Program Generation and Design for Testability for Microprocessors. IEEE Trans. Very Large Scale Integr. Syst. Loganathan Lingappan, Niraj K. Jha
2007	J	`jnl`	Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems. IEEE Trans. Very Large Scale Integr. Syst. Jiong Luo, Niraj K. Jha, Li-Shiuan Peh
2006	J	`jnl`	A Scalable Synthesis Methodology for Application-Specific Processors. IEEE Trans. Very Large Scale Integr. Syst. Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2006	J	`jnl`	A Study of the Energy Consumption Characteristics of Cryptographic Algorithms and Security Protocols. IEEE Trans. Mob. Comput. Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2006	C	`conf`	Active Learning Driven Data Acquisition for Sensor Networks. ISCC Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
2006	J	`jnl`	An Algorithm for Synthesis of Reversible Logic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Pallav Gupta, Abhinav Agrawal, Niraj K. Jha
2006	J	`jnl`	Application-specific heterogeneous multiprocessor synthesis using extensible processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2006	Misc	`conf`	Architectural support for safe software execution on embedded processors. CODES+ISSS Divya Arora, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
2006	—	`conf`	Architectures for efficient face authentication in embedded systems. DATE Designers' Forum Najwa Aaraj, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2006	J	`jnl`	Dynamic Power Optimization Targeting User Delays in Interactive Systems. IEEE Trans. Mob. Comput. Lin Zhong, Niraj K. Jha
2006	J	`jnl`	Energy-Efficient Graphical User Interface Design. IEEE Trans. Mob. Comput. Keith S. Vallerio, Lin Zhong, Niraj K. Jha
2006	J	`jnl`	Hardware-Assisted Run-Time Monitoring for Secure Program Execution on Embedded Processors. IEEE Trans. Very Large Scale Integr. Syst. Divya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2006	A*	`conf`	HybDTM: a coordinated hardware-software approach for dynamic thermal management. DAC Amit Kumar, Li Shang, Li-Shiuan Peh, Niraj K. Jha
2006	Misc	`conf`	Hybrid Custom Instruction and Co-Processor Synthesis Methodology for Extensible Processors. VLSI Design Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2006	Misc	`conf`	Impact of Configurability and Extensibility on IPSec Protocol Execution on Embedded Processors. VLSI Design Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Ruby B. Lee, Niraj K. Jha
2006	Misc	`conf`	Improving the Performance of Automatic Sequential Test Generation by Targeting Hard-to-Test Faults. VLSI Design Loganathan Lingappan, Niraj K. Jha
2006	A*	`conf`	NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture. DAC Wei Zhang, Niraj K. Jha, Li Shang
2006	J	`jnl`	PowerHerd: a distributed scheme for dynamically satisfying peak-power constraints in interconnection networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Li Shang, Li-Shiuan Peh, Niraj K. Jha
2006	J	`jnl`	RTL-Aware Cycle-Accurate Functional Power Estimation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lin Zhong, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2006	—	`conf`	Satisfiability-based framework for enabling side-channel attacks on cryptographic software. DATE Designers' Forum Nachiketh R. Potlapally, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha, Ruby B. Lee
2006	J	`jnl`	Satisfiability-based test generation for nonseparable RTL controller-datapath circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Loganathan Lingappan, Srivaths Ravi, Niraj K. Jha
2006	A*	`conf`	Software architecture exploration for high-performance security processing on a multiprocessor mobile SoC. DAC Divya Arora, Anand Raghunathan, Srivaths Ravi, Murugan Sankaradass, Niraj K. Jha, Srimat T. Chakradhar
2006	Misc	`conf`	State Encoding of Finite-State Machines Targeting Threshold and Majority Logic Based Implementations with Application to Nanotechnologies. VLSI Design Rui Zhang, Niraj K. Jha
2006	J	`jnl`	Temperature-Aware On-Chip Networks. IEEE Micro Li Shang, Li-Shiuan Peh, Amit Kumar, Niraj K. Jha
2006	A	`conf`	Test generation for combinational quantum cellular automata (QCA) circuits. DATE Pallav Gupta, Niraj K. Jha, Loganathan Lingappan
2006	J	`jnl`	Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Loganathan Lingappan, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha, Srimat T. Chakradhar
2006	—	`conf`	Threshold/majority logic synthesis and concurrent error detection targeting nanoelectronic implementations. ACM Great Lakes Symposium on VLSI Rui Zhang, Niraj K. Jha
2006	J	`jnl`	Use of Computation-Unit Integrated Memories in High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2005	—	`conf`	A personal-area network of low-power wireless interfacing devices for handhelds: system and hardware design. Mobile HCI Lin Zhong, Mike Sinclair, Niraj K. Jha
2005	C	`conf`	ALLCN: An Automatic Logic-to-Layout Tool for Carbon Nanotube Based Nanotechnology. ICCD Wei Zhang, Niraj K. Jha
2005	A*	`conf`	Efficient fingerprint-based user authentication for embedded systems. DAC Pallav Gupta, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2005	—	`conf`	Eliminating memory bottlenecks for a JPEG encoder through distributed logic-memory architecture and computation-unit integrated memory. CICC Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2005	A	`conf`	Energy efficiency of handheld computer interfaces: limits, characterization and practice. MobiSys Lin Zhong, Niraj K. Jha
2005	J	`jnl`	Energy macromodeling of embedded operating systems. ACM Trans. Embed. Comput. Syst. Tat Kee Tan, Anand Raghunathan, Niraj K. Jha
2005	Misc	`conf`	Enhancing security through hardware-assisted run-time validation of program data properties. CODES+ISSS Divya Arora, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
2005	J	`jnl`	Generation of distributed logic-memory architectures through high-level synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2005	Misc	`conf`	Heterogeneous and Multi-Level Compression Techniques for Test Volume Reduction in Systems-on-Chip. VLSI Design Loganathan Lingappan, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha, Srimat T. Chakradhar
2005	A*	`conf`	Hybrid simulation for embedded software energy estimation. DAC Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
2005	J	`jnl`	Input space-adaptive optimization for embedded-software synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha
2005	J	`jnl`	Integrated functional partitioning and synthesis for low power distributed systems of systems-on-a-chip. Int. J. Embed. Syst. Yunsi Fei, Niraj K. Jha
2005	J	`jnl`	Interconnect-aware low-power high-level synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lin Zhong, Niraj K. Jha
2005	J	`jnl`	Joint dynamic voltage scaling and adaptive body biasing for heterogeneous distributed real-time embedded systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Le Yan, Jiong Luo, Niraj K. Jha
2005	J	`jnl`	Memory binding for performance optimization of control-flow intensive behavioral descriptions. IEEE Trans. Very Large Scale Integr. Syst. Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha
2005	C	`conf`	Nanotechnology in the Service of Embedded and Ubiquitous Computing. EUC Niraj K. Jha
2005	A	`conf`	Secure Embedded Processing through Hardware-Assisted Run-Time Monitoring. DATE Divya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2005	Misc	`conf`	Synthesis of Application-Specific Heterogeneous Multiprocessor Architectures Using Extensible Processors. VLSI Design Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2005	Misc	`conf`	Synthesis of Majority and Minority Networks and Its Applications to QCA, TPL and SET Based Nanotechnologies. VLSI Design Rui Zhang, Pallav Gupta, Niraj K. Jha
2005	J	`jnl`	Threshold network synthesis and optimization and its application to nanotechnologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Rui Zhang, Pallav Gupta, Lin Zhong, Niraj K. Jha
2005	B	`conf`	Towards a Responsive, Yet Power-ef.cient, Operating System: A Holistic Approach. MASCOTS Le Yan, Lin Zhong, Niraj K. Jha
2005	Misc	`conf`	Unsatisfiability Based Efficient Design for Testability Solution for Register-Transfer Level Circuits. VTS Loganathan Lingappan, Niraj K. Jha
2005	A*	`conf`	User-perceived latency driven voltage scaling for interactive applications. DAC Le Yan, Lin Zhong, Niraj K. Jha
2004	J	`jnl`	A hybrid energy-estimation technique for extensible processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2004	A	`conf`	An Algorithm for Nano-Pipelining of Circuits and Architectures for a Nanotechnology. DATE Pallav Gupta, Niraj K. Jha
2004	C	`conf`	An Automatic Test Pattern Generation Framework for Combinational Threshold Logic Networks. ICCD Pallav Gupta, Rui Zhang, Niraj K. Jha
2004	B	`conf`	An Energy-Aware Framework for Coordinated Dynamic Software Management in Mobile Computers. MASCOTS Yunsi Fei, Lin Zhong, Niraj K. Jha
2004	—	`conf`	An Energy-Aware Synthesis Methodology for OS-Driven Multi-Process Embedded Software. ESA/VLSI Tat Kee Tan, Anand Raghunathan, Niraj K. Jha
2004	A*	`conf`	Automated energy/performance macromodeling of embedded software. DAC Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
2004	J	`jnl`	COWLS: hardware-software cosynthesis of wireless low-power distributed embedded client-server systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Robert P. Dick, Niraj K. Jha
2004	J	`jnl`	Common-case computation: a high-level energy and performance optimization technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ganesh Lakshminarayana, Anand Raghunathan, Kamal S. Khouri, Niraj K. Jha, Sujit Dey
2004	J	`jnl`	Custom-instruction synthesis for extensible-processor platforms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2004	J	`jnl`	DESP: A Distributed Economics-Based Subcontracting Protocol for Computation Distribution in Power-Aware Mobile Ad Hoc Networks. IEEE Trans. Mob. Comput. Li Shang, Robert P. Dick, Niraj K. Jha
2004	Misc	`conf`	Dynamic Power Optimization of Interactive Systems. VLSI Design Lin Zhong, Niraj K. Jha
2004	C	`ed.`	Embedded and Ubiquitous Computing, International Conference EUC 2004, Aizu-Wakamatsu City, Japan, August 25-27, 2004, Proceedings EUC Laurence Tianruo Yang, Minyi Guo, Guang R. Gao, Niraj K. Jha
2004	—	`conf`	Energy-Efficient Graphical User Interface Design. International Conference on Wireless Networks Keith S. Vallerio, Lin Zhong, Niraj K. Jha
2004	Misc	`conf`	Energy-Optimizing Source Code Transformations for OS-driven Embedded Software. VLSI Design Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2004	—	`conf`	Evaluating Conditional Statements in Embedded System Software: Systematic Methodologies for Reducing Energy Consumption. ESA/VLSI Keith S. Vallerio, Niraj K. Jha
2004	A	`conf`	High-level synthesis using computation-unit integrated memories. ICCAD Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2004	J	`jnl`	Input space adaptive design: a high-level methodology for optimizing energy and performance. IEEE Trans. Very Large Scale Integr. Syst. Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha
2004	—	`conf`	Language Selection for Mobile Systems: Java, C, or Both? ESA/VLSI Keith S. Vallerio, Niraj K. Jha
2004	A	`conf`	Power estimation for cycle-accurate functional descriptions of hardware. ICCAD Lin Zhong, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2004	Misc	`conf`	Profiling Driven Computation Reuse: An Embedded Software Synthesis Technique for Energy and Performance Optimization. VLSI Design Weidong Wang, Anand Raghunathan, Niraj K. Jha
2004	J	`jnl`	Register binding-based RTL power management for control-flow intensive designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jiong Luo, Lin Zhong, Yunsi Fei, Niraj K. Jha
2004	J	`jnl`	Resource budgeting for Multiprocess High-level synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Weidong Wang, Anand Raghunathan, Niraj K. Jha, Sujit Dey
2004	A	`conf`	Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies. DATE Rui Zhang, Pallav Gupta, Lin Zhong, Niraj K. Jha
2004	A	`conf`	Synthesis of Reversible Logic. DATE Abhinav Agrawal, Niraj K. Jha
2004	A*	`conf`	Thermal Modeling, Characterization and Management of On-Chip Networks. MICRO Li Shang, Li-Shiuan Peh, Amit Kumar, Niraj K. Jha
2003	A	`conf`	A High-level Interconnect Power Model for Design Space Exploration. ICCAD Pallav Gupta, Lin Zhong, Niraj K. Jha
2003	A	`conf`	A Scalable Application-Specific Processor Synthesis Methodology. ICCAD Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2003	—	`conf`	A comprehensive high-level synthesis system for control-flow intensive behaviors. ACM Great Lakes Symposium on VLSI Weidong Wang, Tat Kee Tan, Jiong Luo, Yunsi Fei, Li Shang, Keith S. Vallerio, Lin Zhong, Anand Raghunathan, Niraj K. Jha
2003	J	`jnl`	A simulation framework for energy-consumption analysis of OS-driven embedded applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tat Kee Tan, Anand Raghunathan, Niraj K. Jha
2003	J	`jnl`	Analysis of power dissipation in embedded systems using real-time operating systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Robert P. Dick, Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha
2003	A	`conf`	Analyzing the energy consumption of security protocols. ISLPED Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2003	A	`conf`	Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Heterogeneous Distributed Real-time Embedded Systems. ICCAD Le Yan, Jiong Luo, Niraj K. Jha
2003	A*	`conf`	Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks. HPCA Li Shang, Li-Shiuan Peh, Niraj K. Jha
2003	A	`conf`	Energy Estimation for Extensible Processors. DATE Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2003	Misc	`conf`	Graphical user interface energy characterization for handheld computers. CASES Lin Zhong, Niraj K. Jha
2003	Misc	`conf`	High-level Synthesis of Multi-process Behavioral Descriptions. VLSI Design Weidong Wang, Niraj K. Jha, Anand Raghunathan, Sujit Dey
2003	J	`jnl`	High-level macro-modeling and estimation techniques for switching activity and power consumption. IEEE Trans. Very Large Scale Integr. Syst. Anand Raghunathan, Sujit Dey, Niraj K. Jha
2003	Misc	`conf`	Power-profile Driven Variable Voltage Sealing for Heterogeneous Distributed Real-time Embedded Systems. VLSI Design Jiong Luo, Niraj K. Jha
2003	A	`conf`	PowerHerd: dynamic satisfaction of peak power constraints in interconnection networks. ICS Li Shang, Li-Shiuan Peh, Niraj K. Jha
2003	A	`conf`	Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems. DATE Jiong Luo, Li-Shiuan Peh, Niraj K. Jha
2003	—	`ch.`	Software Architectural Transformations. Embedded Software for SoC Tat Kee Tan, Anand Raghunathan, Niraj K. Jha
2003	A	`conf`	Software Architectural Transformations: A New Approach to Low Energy Embedded Software. DATE Tat Kee Tan, Anand Raghunathan, Niraj K. Jha
2003	A	`conf`	Synthesis of Heterogeneous Distributed Architectures for Memory-Intensive Applications. ICCAD Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2003	Misc	`conf`	Task Graph Extraction for Embedded System Synthesis. VLSI Design Keith S. Vallerio, Niraj K. Jha
2003	C	`conf`	Test Generation for Non-separable RTL Controller-datapath Circuits using a Satisfiability based Approach. ICCD Loganathan Lingappan, Srivaths Ravi, Niraj K. Jha
2002	—	`conf`	An Economics-based Power-aware Protocol for Computation Distribution in Mobile Ad-Hoc Networks. IASTED PDCS Li Shang, Robert P. Dick, Niraj K. Jha
2002	C	`conf`	Embedded Operating System Energy Analysis and Macro-Modeling. ICCD Tat Kee Tan, Anand Raghunathan, Niraj K. Jha
2002	—	`conf`	Functional Partitioning for Low Power Distributed Systems of Systems-on-a-Chip. ASP-DAC/VLSI Design Yunsi Fei, Niraj K. Jha
2002	—	`conf`	Hardware-Software Co-Synthesis of Low Power Real-Time Distributed Embedded Systems with Dynamically Reconfigurable FPGAs. ASP-DAC/VLSI Design Li Shang, Niraj K. Jha
2002	J	`jnl`	High-level energy macromodeling of embedded software. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tat Kee Tan, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha
2002	A	`conf`	High-level synthesis of distributed logic-memory architectures. ICCAD Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2002	J	`jnl`	High-level test compaction techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
2002	—	`conf`	Input Space Adaptive Embedded Software Synthesis. ASP-DAC/VLSI Design Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha
2002	A	`conf`	Interconnect-aware high-level synthesis for low power. ICCAD Lin Zhong, Niraj K. Jha
2002	J	`jnl`	Leakage power analysis and reduction during behavioral synthesis. IEEE Trans. Very Large Scale Integr. Syst. Kamal S. Khouri, Niraj K. Jha
2002	Misc	`conf`	Low Power Distributed Embedded Systems: Dynamic Voltage Scaling and Synthesis. HiPC Jiong Luo, Niraj K. Jha
2002	J	`jnl`	Power-efficient Interconnection Networks: Dynamic Voltage Scaling with Links. IEEE Comput. Archit. Lett. Li Shang, Li-Shiuan Peh, Niraj K. Jha
2002	C	`conf`	Register Binding Based Power Management for High-level Synthesis of Control-Flow Intensive Behaviors. ICCD Lin Zhong, Jiong Luo, Yunsi Fei, Niraj K. Jha
2002	—	`conf`	Static and Dynamic Variable Voltage Scheduling Algorithms for Real-Time Heterogeneous Distributed Embedded Systems. ASP-DAC/VLSI Design Jiong Luo, Niraj K. Jha
2002	A	`conf`	Synthesis of custom processors based on extensible platforms. ICCAD Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2002	—	`conf`	Task graph transformation to aid system synthesis. ISCAS (4) Keith S. Vallerio, Niraj K. Jha
2002	J	`jnl`	Test synthesis of systems-on-a-chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Srivaths Ravi, Niraj K. Jha
2001	A*	`conf`	Battery-Aware Static Scheduling for Distributed Real-Time Embedded Systems. DAC Jiong Luo, Niraj K. Jha
2001	J	`jnl`	Clock selection for performance optimization of control-flowintensive behaviors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kamal S. Khouri, Niraj K. Jha
2001	A	`conf`	Fast test generation for circuits with RTL and gate-level views. ITC Srivaths Ravi, Niraj K. Jha
2001	J	`jnl`	Fault-diagnosis-based technique for establishing RTL and gate-levelcorrespondences. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Srivaths Ravi, Indradeep Ghosh, Vamsi Boppana, Niraj K. Jha
2001	C	`conf`	High-Level Power Modeling of CPLDs and FPGAs. ICCD Li Shang, Niraj K. Jha
2001	A*	`conf`	High-level Software Energy Macro-modeling. DAC Tat Kee Tan, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha
2001	A*	`conf`	Input Space Adaptive Design: A High-level Methodology for Energy and Performance Optimization. DAC Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha
2001	A	`conf`	Low Power System Scheduling and Synthesis. ICCAD Niraj K. Jha
2001	Misc	`conf`	Synthesis of System-on-a-chip for Testability. VLSI Design Srivaths Ravi, Niraj K. Jha
2001	J	`jnl`	TAO: regular expression-based register-transfer level testability analysis and optimization. IEEE Trans. Very Large Scale Integr. Syst. Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
2001	J	`jnl`	Testing of core-based systems-on-a-chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
2000	A	`conf`	: Reducing test application time in high-level test generation. ITC Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
2000	J	`jnl`	A BIST scheme for RTL circuits based on symbolic testabilityanalysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik
2000	C	`conf`	A Technique for Identifying RTL and Gate-Level Correspondences. ICCD Srivaths Ravi, Niraj K. Jha, Indradeep Ghosh, Vamsi Boppana
2000	J	`jnl`	A fast and low-cost testing technique for core-based system-chips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Indradeep Ghosh, Sujit Dey, Niraj K. Jha
2000	J	`jnl`	Behavioral Synthesis of Fault Secure Controller/Datapaths Based on Aliasing Probability Analysis. IEEE Trans. Computers Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha
2000	Misc	`conf`	COWLS: Hardware-Software Co-Synthesis of Distributed Wireless Low-Power Embedded Client-Server Systems. VLSI Design Robert P. Dick, Niraj K. Jha
2000	Misc	`conf`	Clock Selection for Performance Optimization of Control-Flow Intensive Behaviors. VLSI Design Kamal S. Khouri, Niraj K. Jha
2000	J	`jnl`	Incorporating speculative execution into scheduling ofcontrol-flow-intensive designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha
2000	C	`conf`	Leakage Power Analysis and Reduction during Behavioral Synthesis. ICCD Kamal S. Khouri, Niraj K. Jha
2000	A*	`conf`	Power analysis of embedded operating systems. DAC Robert P. Dick, Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha
2000	A	`conf`	Power-Conscious Joint Scheduling of Periodic Task Graphs and Aperiodic Tasks in Distributed Real-Time Embedded Systems. ICCAD Jiong Luo, Niraj K. Jha
2000	J	`jnl`	TAO-BIST: A framework for testability analysis and optimization forbuilt-in self-test of RTL circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
1999	A	`conf`	A framework for testing core-based systems-on-a-chip. ICCAD Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
1999	J	`jnl`	A low overhead design for testability and test generation technique for core-based systems-on-a-chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Indradeep Ghosh, Niraj K. Jha, Sujit Dey
1999	J	`jnl`	COFTA: Hardware-Software Co-Synthesis of Heterogeneous Distributed Embedded Systems. IEEE Trans. Computers Bharat P. Dave, Niraj K. Jha
1999	J	`jnl`	COSYN: Hardware-software co-synthesis of heterogeneous distributed embedded systems. IEEE Trans. Very Large Scale Integr. Syst. Bharat P. Dave, Ganesh Lakshminarayana, Niraj K. Jha
1999	A*	`conf`	Common-Case Computation: A High-Level Technique for Power and Performance Optimization. DAC Ganesh Lakshminarayana, Anand Raghunathan, Kamal S. Khouri, Niraj K. Jha, Sujit Dey
1999	J	`jnl`	Controller-based power management for control-flow intensive designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sujit Dey, Anand Raghunathan, Niraj K. Jha, Kazutoshi Wakabayashi
1999	J	`jnl`	Corrections to "mogac: a multiobjective genetic algorithm for hardware-software cosynthesis of distributed embedded systems". IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Robert P. Dick, Niraj K. Jha
1999	J	`jnl`	FACT: a framework for applying throughput and power optimizing transformations to control-flow-intensive behavioral descriptions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ganesh Lakshminarayana, Niraj K. Jha
1999	J	`jnl`	Hierarchical test generation and design for testability methods for ASPPs and ASIPs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha
1999	J	`jnl`	High-level synthesis of low-power control-flow intensive circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha
1999	J	`jnl`	High-level synthesis of power-optimized and area-optimized circuits from hierarchical data-flow intensive behaviors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ganesh Lakshminarayana, Niraj K. Jha
1999	A	`conf`	MOCSYN: Multiobjective Core-Based Single-Chip System Synthesis. DATE Robert P. Dick, Niraj K. Jha
1999	A	`conf`	Memory binding for performance optimization of control-flow intensive behaviors. ICCAD Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha
1999	J	`jnl`	Power management in high-level synthesis. IEEE Trans. Very Large Scale Integr. Syst. Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey
1999	J	`jnl`	Register transfer level power optimization with emphasis on glitch analysis and reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Anand Raghunathan, Sujit Dey, Niraj K. Jha
1999	J	`jnl`	Safety and Reliability Driven Task Allocation in Distributed Systems. IEEE Trans. Parallel Distributed Syst. Santhanam Srinivasan, Niraj K. Jha
1999	Misc	`conf`	TAO-BIST: A Framework for Testability Analysis and Optimizationb of RTL Circuits for BIST. VTS Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
1999	J	`jnl`	Wavesched: a novel scheduling technique for control-flow intensive designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ganesh Lakshminarayana, Kamal S. Khouri, Niraj K. Jha
1998	A*	`conf`	A BIST Scheme for RTL Controller-Data Paths Based on Symbolic Testability Analysis. DAC Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik
1998	A*	`conf`	A Fast and Low Cost Testing Technique for Core-Based System-on-Chip. DAC Indradeep Ghosh, Sujit Dey, Niraj K. Jha
1998	Misc	`conf`	A Power Management Methodology for High-Level Synthesis. VLSI Design Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey
1998	J	`jnl`	A design-for-testability technique for register-transfer level circuits using control/data flow extraction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha
1998	A	`conf`	CASPER: Concurrent Hardware-Software Co-Synthesis of Hard Real-Time Aperiodic and Periodic Specifications of Embedded System Architectures. DATE Bharat P. Dave, Niraj K. Jha
1998	Misc	`conf`	COHRA: Hardware-Software Co-Synthesis of Hierarchical Distributed Embedded System Architectures. VLSI Design Bharat P. Dave, Niraj K. Jha
1998	J	`jnl`	COHRA: hardware-software cosynthesis of hierarchical heterogeneous distributed embedded systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Bharat P. Dave, Niraj K. Jha
1998	A	`conf`	CORDS: hardware-software co-synthesis of reconfigurable real-time distributed embedded systems. ICCAD Robert P. Dick, Niraj K. Jha
1998	A	`conf`	Fast high-level power estimation for control-flow intensive design. ISLPED Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha
1998	J	`jnl`	Guest Editorial. J. Electron. Test. Niraj K. Jha
1998	—	`book`	High-Level Power Analysis and Optimization. Anand Raghunathan, Niraj K. Jha, Sujit Dey
1998	J	`jnl`	High-level test synthesis: a survey. Integr. Indradeep Ghosh, Niraj K. Jha
1998	A	`conf`	IMPACT: A High-Level Synthesis System for Low Power Control-Flow Intensive Circuits. DATE Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha
1998	A*	`conf`	Incorporating Speculative Execution into Scheduling of Control-Flow Intensive Behavioral Descriptions. DAC Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha
1998	J	`jnl`	Integration of hierarchical test generation with behavioral synthesis of controller and data path circuits. IEEE Trans. Very Large Scale Integr. Syst. Sandeep Bhatia, Niraj K. Jha
1998	J	`jnl`	MOGAC: a multiobjective genetic algorithm for hardware-software cosynthesis of distributed embedded systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Robert P. Dick, Niraj K. Jha
1998	A	`conf`	Removal of memory access bottlenecks for scheduling control-flow intensive behavioral descriptions. ICCAD Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
1998	A*	`conf`	Synthesis of Power-Optimized and Area-Optimized Circuits from Hierarchical Behavioral Descriptions. DAC Ganesh Lakshminarayana, Niraj K. Jha
1998	A	`conf`	TAO: regular expression based high-level testability analysis and optimization. ITC Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
1998	A	`conf`	Transforming control-flow intensive designs to facilitate power management. ICCAD Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey
1997	A	`conf`	A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems. ITC Indradeep Ghosh, Niraj K. Jha, Sujit Dey
1997	J	`jnl`	Analysis and Randomized Design of Algorithm-Based Fault Tolerant Multiprocessor Systems Under an Extended Model. IEEE Trans. Parallel Distributed Syst. Shalini Yajnik, Niraj K. Jha
1997	—	`conf`	COFTA: Hardware-Software Co-Synthesis of Heterogeneous Distributed Embedded System Architectures for Low Overhead Fault Tolerance. FTCS Bharat P. Dave, Niraj K. Jha
1997	A*	`conf`	COSYN: Hardware-Software Co-Synthesis of Embedded Systems. DAC Bharat P. Dave, Ganesh Lakshminarayana, Niraj K. Jha
1997	J	`jnl`	Design for hierarchical testability of RTL circuits obtained by behavioral synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha
1997	J	`jnl`	Graceful Degradation in Algorithm-Based Fault Tolerant Multiprocessor Systems. IEEE Trans. Parallel Distributed Syst. Shalini Yajnik, Niraj K. Jha
1997	A*	`conf`	Hierarchical Test Generation and Design for Testability of ASPPs and ASIPs. DAC Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha
1997	A	`conf`	MOGAC: a multiobjective genetic algorithm for the co-synthesis of hardware-software embedded systems. ICCAD Robert P. Dick, Niraj K. Jha
1997	A*	`conf`	Power Management Techniques for Control-Flow Intensive Designs. DAC Anand Raghunathan, Sujit Dey, Niraj K. Jha, Kazutoshi Wakabayashi
1997	J	`jnl`	SCALP: an iterative-improvement-based low-power data path synthesis system. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Anand Raghunathan, Niraj K. Jha
1997	J	`jnl`	Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Steven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng
1997	A	`conf`	Wavesched: a novel scheduling technique for control-flow intensive behavioral descriptions. ICCAD Ganesh Lakshminarayana, Kamal S. Khouri, Niraj K. Jha
1996	A	`conf`	A design for testability technique for RTL circuits using control/data flow extraction. ICCAD Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha
1996	—	`conf`	Behavioral Synthesis of Fault Secure Controller?Datapaths using Aliasing Probability Analysis. FTCS Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha
1996	A	`conf`	Controller re-specification to minimize switching activity in controller/data path circuits. ISLPED Anand Raghunathan, Sujit Dey, Niraj K. Jha, Kazutoshi Wakabayashi
1996	A*	`conf`	Glitch Analysis and Reduction in Register Transfer Level. DAC Anand Raghunathan, Sujit Dey, Niraj K. Jha
1996	Misc	`conf`	Hardware-Software Co-Design for Test: It's the Last Straw! VTS J. El-Ziq, Najmi T. Jarwala, Niraj K. Jha, Peter Marwedel, Christos A. Papachristou, Janusz Rajski, John W. Sheppard
1996	A	`conf`	Register-transfer level estimation techniques for switching activity and power consumption. ICCAD Anand Raghunathan, Sujit Dey, Niraj K. Jha
1996	J	`jnl`	Synthesis for parallel scan: applications to partial scan and robust path-delay fault testability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sandeep Bhatia, Niraj K. Jha
1995	C	`conf`	An ILP Formulation for Low Power Based on Minimizing Switched Capacitance During Data Path Allocation. ISCAS Anand Raghunathan, Niraj K. Jha
1995	A	`conf`	An iterative improvement algorithm for low power data path synthesis. ICCAD Anand Raghunathan, Niraj K. Jha
1995	C	`conf`	Design for hierarchical testability of RTL circuits obtained by behavioral synthesis. ICCD Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha
1995	—	`conf`	Hardware-software co-synthesis of fault-tolerant real-time distributed embedded systems. EURO-DAC Santhanam Srinivasan, Niraj K. Jha
1995	Misc	`conf`	Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability. VLSI Design Steven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng
1995	—	`conf`	Task Allocation for Safety and Reliability in Distributed Systems. ICPP (2) Santhanam Srinivasan, Niraj K. Jha
1994	J	`jnl`	A Totally Self-Checking Checker for a Parallel Unordered Coding Scheme. IEEE Trans. Computers Steven W. Burns, Niraj K. Jha
1994	J	`jnl`	Algorithm-Based Fault Tolerance for FFT Networks. IEEE Trans. Computers Sying-Jyan Wang, Niraj K. Jha
1994	C	`conf`	Behavioral Synthesis for Hierarchical Testability of Controller/Data Path Circuits with Conditional Branches. ICCD Sandeep Bhatia, Niraj K. Jha
1994	C	`conf`	Behavioral Synthesis for low Power. ICCD Anand Raghunathan, Niraj K. Jha
1994	J	`jnl`	Design of Algorithm-Based Fault-Tolerant Multiprocessor Systems for Concurrent Error Detection and Fault Diagnosis. IEEE Trans. Parallel Distributed Syst. Bapiraju Vinnakota, Niraj K. Jha
1994	—	`conf`	Genesis: A Behavioral Synthesis System for Hierarchical Testability. EDAC-ETC-EUROASIC Sandeep Bhatia, Niraj K. Jha
1994	C	`conf`	Graceful Degradation in Algorithm-Based Fault Tolerant Multiprocessor Systems. ISCAS Shalini Yajnik, Niraj K. Jha
1994	J	`jnl`	Partitioned Encoding Schemes for Algorithm-Based Fault Tolerance in Massively Parallel Systems. IEEE Trans. Parallel Distributed Syst. Jennifer Rexford, Niraj K. Jha
1994	C	`conf`	Synthesis of Fault Tolerant Architectures for Molecular Dynamics. ISCAS Shalini Yajnik, Niraj K. Jha
1993	A	`conf`	A Conditional Resource-Sharing Method for Behavior Synthesis of Highly- Testable Data Paths. ITC Tien-Chien Lee, Niraj K. Jha, Wayne H. Wolf
1993	A*	`conf`	Behavioral Synthesis of Highly Testable Data Paths under the Non-Scan and Partial Scan Environments. DAC Tien-Chien Lee, Niraj K. Jha, Wayne H. Wolf
1993	J	`jnl`	Design and synthesis of self-checking VLSI circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Niraj K. Jha, Sying-Jyan Wang
1993	—	`conf`	Design of Algorithm-Based Fault Tolerant Systems With In-System Checks. ICPP (1) Shalini Yajnik, Niraj K. Jha
1993	J	`jnl`	Diagnosability and Diagnosis of Algorithm-Based Fault-Tolerant Systems. IEEE Trans. Computers Bapiraju Vinnakota, Niraj K. Jha
1993	J	`jnl`	Easily testable nonrestoring and restoring gate-level cellular array dividers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Niraj K. Jha, Abha Ahuja
1993	C	`conf`	Efficient Diagnosis in Algorithm-Based Fault Tolerant Multiprocessor Systems. ICCD Santhanam Srinivasan, Niraj K. Jha
1993	J	`jnl`	Fault Detection in CVS Parity Trees with Application to Strongly Self-Checking Parity and Two-Rail Checkers. IEEE Trans. Computers Niraj K. Jha
1993	J	`jnl`	Optimal Design of Checks for Error Detection and Location in Fault-Tolerant Multiprocessor Systems. IEEE Trans. Computers Ramesh K. Sitaraman, Niraj K. Jha
1993	J	`jnl`	Synthesis of Algorithm-Based Fault-Tolerant Systems from Dependence Graphs. IEEE Trans. Parallel Distributed Syst. Bapiraju Vinnakota, Niraj K. Jha
1993	C	`conf`	Synthesis of Sequential Circuits for Easy Testability Through Performance-Oriented Parallel Partial Scan. ICCD Sandeep Bhatia, Niraj K. Jha
1993	Misc	`conf`	Synthesis of Sequential Circuits for Robust Path Delay Fault Testability. VLSI Design Sandeep Bhatia, Niraj K. Jha
1992	Misc	`conf`	A totally self-checking checker for a parallel unordered coding scheme. VTS Steven W. Burns, Niraj K. Jha
1992	C	`conf`	Behavioral Synthesis for Easy Testability in Data Path Allocation. ICCD Tien-Chien Lee, Wayne H. Wolf, Niraj K. Jha, John M. Acken
1992	A	`conf`	Behavioral synthesis for easy testability in data path scheduling. ICCAD Tien-Chien Lee, Wayne H. Wolf, Niraj K. Jha
1992	—	`conf`	Design and Analysis of Fault-Detecting and Fault-Locating Schedules for Computation DAGs. IPPS Shalini Yajnik, Niraj K. Jha
1992	C	`conf`	Multiple Input Bridging Fault Detection in CMOS Sequential Circuits. ICCD Niraj K. Jha, Sying-Jyan Wang, Phillip C. Gripka
1992	—	`conf`	Synthesis of Multi-Level Combinational Circuits for Complete Robust Path Delay Fault Testability. FTCS Niraj K. Jha, Irith Pomeranz, Sudhakar M. Reddy, Robert J. Miller
1991	J	`jnl`	A new transition count method for testing of logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Konstantinos I. Diamantaras, Niraj K. Jha
1991	C	`conf`	Design and Synthesis of Self-Checking VLSI Circuits and Systems. ICCD Niraj K. Jha, Sying-Jyan Wang
1991	J	`jnl`	Design of C-testable DCVS binary array dividers. IEEE J. Solid State Circuits Qiao Tong, Niraj K. Jha
1991	—	`conf`	Design of Multiprocessor Systems for Concurrent Error Detection and Fault Diagnosis. FTCS Bapiraju Vinnakota, Niraj K. Jha
1991	J	`jnl`	Design of robustly testable combinational logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sandip Kundu, Sudhakar M. Reddy, Niraj K. Jha
1991	J	`jnl`	Easily testable gate-level and DCVS multipliers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andres R. Takach, Niraj K. Jha
1991	—	`conf`	MACHETE: synthesis of sequential machines for easy testability. EURO-DAC Bapiraju Vinnakota, Niraj K. Jha
1991	—	`conf`	Optimal Design of Checks for Error Detection and Location in Fault Tolerant Multiprocessors Systems. Fault-Tolerant Computing Systems Ramesh K. Sitaraman, Niraj K. Jha
1991	J	`jnl`	Robustly testable static CMOS parity trees derived from binary decision diagrams. IEEE J. Solid State Circuits Niraj K. Jha, Qiao Tong
1991	J	`jnl`	Totally self-checking checker designs for Bose-Lin, Bose, and Blaum codes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Niraj K. Jha
1990	—	`conf`	A dependence graph-based approach to the design of algorithm-based fault tolerant systems. FTCS Bapiraju Vinnakota, Niraj K. Jha
1990	C	`conf`	Design of robustly testable static CMOS parity trees derived from binary decision diagrams. ICCD Niraj K. Jha, Carol Q. Tong
1990	—	`conf`	Detection of multiple input bridging and stuck-on faults in CMOS logic circuits using current monitoring. EURO-DAC Niraj K. Jha, Qiao Tong
1990	J	`jnl`	Strong fault-secure and strongly self-checking domino-CMOS implementations of totally self-checking circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Niraj K. Jha
1990	J	`jnl`	Testing of differential cascode voltage switch one-count generators. IEEE J. Solid State Circuits Niraj K. Jha
1990	J	`jnl`	Testing of multiple-output domino logic (MODL) CMOS circuits. IEEE J. Solid State Circuits Niraj K. Jha, Qiao Tong
1990	J	`jnl`	Testing of zipper CMOS logic circuits. IEEE J. Solid State Circuits Qiao Tong, Niraj K. Jha
1989	J	`jnl`	A totally self-checking checker for Borden's code. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Niraj K. Jha
1989	J	`jnl`	Comments on 'A MOS implementation of totally self-checking checker for the 1-out-of-3 code'. IEEE J. Solid State Circuits Niraj K. Jha
1989	C	`conf`	Design of sufficiently strongly self-checking embedded checkers for systematic and separable codes. ICCD Niraj K. Jha
1989	—	`conf`	Fault detection in CVS parity trees: application in SSC CVS parity and two-rail checkers. FTCS Niraj K. Jha
1989	J	`jnl`	Separable codes for detecting unidirectional errors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Niraj K. Jha
1988	C	`conf`	A new class of symmetric error correcting / unidirectional error detecting codes. ICCD Niraj K. Jha
1988	J	`jnl`	A universal test set for CMOS circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Gopal Gupta, Niraj K. Jha
1988	J	`jnl`	Multiple Stuck-Open Fault Detection in CMOS Logic Circuits. IEEE Trans. Computers Niraj K. Jha
1988	A	`conf`	On the design of robust multiple fault testable CMOS combinational logic circuits. ICCAD Sandip Kundu, Sudhakar M. Reddy, Niraj K. Jha
1988	J	`jnl`	Testing for multiple faults in domino-CMOS logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Niraj K. Jha
1986	A	`conf`	Detecting Multiple Faults in CMOS Circuits. ITC Niraj K. Jha
1985	J	`jnl`	Design of Testable CMOS Logic Circuits Under Arbitrary Delays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Niraj K. Jha, Jacob A. Abraham