Ning Wang - RankMe

12 papers A* 5Journal 7

Year	Rank	Type	Title / Venue / Authors
2026	A*	`conf`	FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification. AAAI Gwok-Waa Wan, SamZaak Wong, Shengchu Su, Chenxu Niu, Ning Wang, Xinlai Wan, Qixiang Chen, Mengnv Xing, Jingyi Zhang, Jianmin Ye, Yubo Wang, Rongchang Song, Tao Ni, Qiang Xu, Nan Guan, Zhe Jiang, Xi Wang, Yong Chen, Jun Yang
2025	J	`jnl`	ARSP: Automated Repair of Verilog Designs via Semantic Partitioning. CoRR Bingkun Yao, Ning Wang, Xiangfeng Liu, Yuxin Du, Yuchen Hu, Hong Gao, Zhe Jiang, Nan Guan
2025	A*	`conf`	Insights from Rights and Wrongs: A Large Language Model for Solving Assertion Failures in RTL Design. DAC Jie Zhou, Youshu Ji, Ning Wang, Yuchen Hu, Xinyao Jiao, Bingkun Yao, Xinwei Fang, Shuai Zhao, Nan Guan, Zhe Jiang
2025	A*	`conf`	Insights from Rights and Wrongs: A Large Language Model for Solving Assertion Failures in RTL Design. DAC Jie Zhou, Youshu Ji, Ning Wang, Yuchen Hu, Xinyao Jiao, Bingkun Yao, Xinwei Fang, Shuai Zhao, Nan Guan, Zhe Jiang
2025	J	`jnl`	Insights from Rights and Wrongs: A Large Language Model for Solving Assertion Failures in RTL Design. CoRR Jie Zhou, Youshu Ji, Ning Wang, Yuchen Hu, Xinyao Jiao, Bingkun Yao, Xinwei Fang, Shuai Zhao, Nan Guan, Zhe Jiang
2025	J	`jnl`	Insights from Verification: Training a Verilog Generation LLM with Reinforcement Learning with Testbench Feedback. CoRR Ning Wang, Bingkun Yao, Jie Zhou, Yuchen Hu, Xi Wang, Nan Guan, Zhe Jiang
2025	A*	`conf`	Location is Key: Leveraging LLM for Functional Bug Localization in Verilog Design. DAC Bingkun Yao, Ning Wang, Jie Zhou, Xi Wang, Hong Gao, Zhe Jiang, Nan Guan
2025	A*	`conf`	UVLLM: An Automated Universal RTL Verification Framework using LLMs. DAC Yuchen Hu, Junhao Ye, Ke Xu, Jialin Sun, Shiyue Zhang, Xinyao Jiao, Dingrong Pan, Jie Zhou, Ning Wang, Weiwei Shan, Xinwei Fang, Xi Wang, Nan Guan, Zhe Jiang
2025	J	`jnl`	VeriDebug: A Unified LLM for Verilog Debugging via Contrastive Embedding and Guided Correction. CoRR Ning Wang, Bingkun Yao, Jie Zhou, Yuchen Hu, Xi Wang, Nan Guan, Zhe Jiang
2024	J	`jnl`	Large Language Model for Verilog Generation with Golden Code Feedback. CoRR Ning Wang, Bingkun Yao, Jie Zhou, Xi Wang, Zhe Jiang, Nan Guan
2024	J	`jnl`	Location is Key: Leveraging Large Language Model for Functional Bug Localization in Verilog. CoRR Bingkun Yao, Ning Wang, Jie Zhou, Xi Wang, Hong Gao, Zhe Jiang, Nan Guan
2024	J	`jnl`	UVLLM: An Automated Universal RTL Verification Framework using LLMs. CoRR Yuchen Hu, Junhao Ye, Ke Xu, Jialin Sun, Shiyue Zhang, Xinyao Jiao, Dingrong Pan, Jie Zhou, Ning Wang, Weiwei Shan, Xinwei Fang, Xi Wang, Nan Guan, Zhe Jiang