Nimish Shah

27 papers A* 3A 2B 2Journal 14Unranked 6
YearRankTypeTitle / Venue / Authors
2025 J jnl
AIA: A Customized Multi-Core RISC-V SoC for Discrete Sampling Workloads in 16 nm.
IEEE J. Solid State Circuits
Shirui Zhao, Nimish Shah, Wannes Meert, Marian Verhelst
2025 J jnl
Decoupled Control Flow and Data Access in RISC-V GPGPUs.
CoRR
Giuseppe Maria Sarda, Nimish Shah, Abubakr Nada, Debjyoti Bhattacharjee, Marian Verhelst
2024 J jnl
Optimising GPGPU Execution Through Runtime Micro-Architecture Parameter Analysis.
CoRR
Giuseppe Maria Sarda, Nimish Shah, Debjyoti Bhattacharjee, Peter Debacker, Marian Verhelst
2023 — conf
Optimising GPGPU Execution Through Runtime Micro-Architecture Parameter Analysis.
IISWC
Giuseppe Maria Sarda, Nimish Shah, Debjyoti Bhattacharjee, Peter Debacker, Marian Verhelst
2022 A* conf
DPU-v2: Energy-efficient execution of irregular directed acyclic graphs.
MICRO
Nimish Shah, Wannes Meert, Marian Verhelst
2022 J jnl
DPU-v2: Energy-efficient execution of irregular directed acyclic graphs.
CoRR
Nimish Shah, Wannes Meert, Marian Verhelst
2022 J jnl
DPU: DAG Processing Unit for Irregular Graphs With Precision-Scalable Posit Arithmetic in 28 nm.
IEEE J. Solid State Circuits
Nimish Shah, Laura Isabel Galindez Olascoaga, Shirui Zhao, Wannes Meert, Marian Verhelst
2022 A conf
Discrete Samplers for Approximate Inference in Probabilistic Machine Learning.
DATE
Shirui Zhao, Nimish Shah, Wannes Meert, Marian Verhelst
2022 J jnl
GraphOpt: Constrained-Optimization-Based Parallelization of Irregular Graphs.
IEEE Trans. Parallel Distributed Syst.
Nimish Shah, Wannes Meert, Marian Verhelst
2021 — conf
9.4 PIU: A 248GOPS/W Stream-Based Processor for Irregular Probabilistic Inference Networks Using Precision-Scalable Posit Arithmetic in 28nm.
ISSCC
Nimish Shah, Laura Isabel Galindez Olascoaga, Shirui Zhao, Wannes Meert, Marian Verhelst
2021 J jnl
Acceleration of probabilistic reasoning through custom processor architecture.
CoRR
Nimish Shah, Laura Isabel Galindez Olascoaga, Wannes Meert, Marian Verhelst
2021 J jnl
DPU: DAG Processing Unit for Irregular Graphs with Precision-Scalable Posit Arithmetic in 28nm.
CoRR
Nimish Shah, Laura Isabel Galindez Olascoaga, Shirui Zhao, Wannes Meert, Marian Verhelst
2021 J jnl
GRAPHOPT: constrained optimization-based parallelization of irregular graphs.
CoRR
Nimish Shah, Wannes Meert, Marian Verhelst
2021 J jnl
ProbLP: A framework for low-precision probabilistic inference.
CoRR
Nimish Shah, Laura Isabel Galindez Olascoaga, Wannes Meert, Marian Verhelst
2020 A conf
Acceleration of probabilistic reasoning through custom processor architecture.
DATE
Nimish Shah, Laura Isabel Galindez Olascoaga, Wannes Meert, Marian Verhelst
2020 B conf
Discriminative Bias for Learning Probabilistic Sentential Decision Diagrams.
IDA
Laura Isabel Galindez Olascoaga, Wannes Meert, Nimish Shah, Guy Van den Broeck, Marian Verhelst
2020 — conf
Dynamic Complexity Tuning for Hardware-Aware Probabilistic Circuits.
IoT Streams/ITEM@PKDD/ECML
Laura Isabel Galindez Olascoaga, Wannes Meert, Nimish Shah, Marian Verhelst
2019 — conf
On Hardware-Aware Probabilistic Frameworks for Resource Constrained Embedded Applications.
EMC2@NeurIPS
Laura Isabel Galindez Olascoaga, Wannes Meert, Nimish Shah, Guy Van den Broeck, Marian Verhelst
2019 A* conf
ProbLP: A framework for low-precision probabilistic inference.
DAC
Nimish Shah, Laura Isabel Galindez Olascoaga, Wannes Meert, Marian Verhelst
2019 A* conf
Towards Hardware-Aware Tractable Learning of Probabilistic Models.
NeurIPS
Laura Isabel Galindez Olascoaga, Wannes Meert, Nimish Shah, Marian Verhelst, Guy Van den Broeck
2018 J jnl
Runtime Programmable and Memory Bandwidth Optimized FPGA-Based Coprocessor for Deep Convolutional Neural Network.
IEEE Trans. Neural Networks Learn. Syst.
Nimish Shah, Paragkumar Chaudhari, Kuruvilla Varghese
2012 — conf
Scalable hierarchical floorplanning for fast physical prototyping of systems-on-chip.
ISPD
Renshen Wang, Nimish Shah
2009 — conf
Facial Features Classification Using the Temporal Correlation Matrix Memory (TCMML).
SoCPaR
Nimish Shah
2007 B conf
The Improved Correlation Matrix Memory (CMML).
IJCNN
Nimish Shah, Simon O'Keefe, Jim Austin
2005 J jnl
"Rippling: Meta-Level Guidance for Mathematical Reasoning, " by Alan Bundy, David Basin, Dieter Hutter, and Andrew Ireland, Cambridge University Press, 2005.
J. Autom. Reason.
Nimish Shah
2004 J jnl
Knowledge Representation, Reasoning and Declarative Problem Solving by C. Baral, Cambridge University Press, 2003.
J. Funct. Program.
Nimish Shah
2004 J jnl
Program Construction: Calculating Implementations from Specifications by R.C. Backhouse, John Wiley & Sons, 2004.
J. Funct. Program.
Nimish Shah