Nils Wistoff

33 papers A* 1A 1C 1Journal 22Unranked 8
YearRankTypeTitle / Venue / Authors
2025 J jnl
A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications.
CoRR
Angelo Garofalo, Alessandro Ottaviano, Matteo Perotti, Thomas Benz, Yvan Tortorella, Robert Balas, Michael Rogenmoser, Chi Zhang, Luca Bertaccini, Nils Wistoff, Maicol Ciani, Cyril Koenig, Mattia Sinigaglia, Luca Valente, Paul Scheffler, Manuel Eggimann, Matheus A. Cavalcante, Francesco Restuccia, Alessandro Biondi, Francesco Conti, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2025 J jnl
A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications.
IEEE Trans. Circuits Syst. II Express Briefs
Angelo Garofalo, Alessandro Ottaviano, Matteo Perotti, Thomas Benz, Yvan Tortorella, Robert Balas, Michael Rogenmoser, Chi Zhang, Luca Bertaccini, Nils Wistoff, Maicol Ciani, Cyril Koenig, Mattia Sinigaglia, Luca Valente, Paul Scheffler, Manuel Eggimann, Matheus A. Cavalcante, Francesco Restuccia, Alessandro Biondi, Francesco Conti, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2025 — conf
AraOS: Analyzing the Impact of Virtual Memory Management on Vector Unit Performance.
CF (Companion)
Matteo Perotti, Vincenzo Maisto, Moritz Imfeld, Nils Wistoff, Alessandro Cilardo, Luca Benini
2025 J jnl
AraOS: Analyzing the Impact of Virtual Memory Management on Vector Unit Performance.
CoRR
Matteo Perotti, Vincenzo Maisto, Moritz Imfeld, Nils Wistoff, Alessandro Cilardo, Luca Benini
2025 J jnl
ArtistIC: An Open-Source Toolchain for Top-Metal IC Art and Ultra-High-Fidelity GDSII Renders.
CoRR
Thomas Benz, Paul Scheffler, Nils Wistoff, Philippe Sauter, Beat Muheim, Luca Benini
2025 J jnl
CVA6S+: A Superscalar RISC-V Core with High-Throughput Memory Architecture.
CoRR
Riccardo Tedeschi, Gianmarco Ottavi, Côme Allart, Nils Wistoff, Zexin Fu, Filippo Grillotti, Fabio De Ambroggi, Elio Guidetti, Jean-Baptiste Rigaud, Olivier Potin, Jean-Roch Coulon, César Fuguet, Luca Benini, Davide Rossi
2025 J jnl
Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12-nm FinFET.
IEEE J. Solid State Circuits
Paul Scheffler, Thomas Benz, Viviane Potocnik, Tim Fischer, Luca Colagrande, Nils Wistoff, Yichao Zhang, Luca Bertaccini, Gianmarco Ottavi, Manuel Eggimann, Matheus A. Cavalcante, Gianna Paulin, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2025 J jnl
Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12nm FinFET.
CoRR
Paul Scheffler, Thomas Benz, Viviane Potocnik, Tim Fischer, Luca Colagrande, Nils Wistoff, Yichao Zhang, Luca Bertaccini, Gianmarco Ottavi, Manuel Eggimann, Matheus A. Cavalcante, Gianna Paulin, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2025 — conf
Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution.
CF
Zexin Fu, Riccardo Tedeschi, Gianmarco Ottavi, Nils Wistoff, César Fuguet, Davide Rossi, Luca Benini
2025 J jnl
Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution.
CoRR
Zexin Fu, Riccardo Tedeschi, Gianmarco Ottavi, Nils Wistoff, César Fuguet, Davide Rossi, Luca Benini
2024 J jnl
A Heterogeneous RISC-V Based SoC for Secure Nano-UAV Navigation.
IEEE Trans. Circuits Syst. I Regul. Pap.
Luca Valente, Alessandro Nadalini, Asif Hussain Chiralil Veeran, Mattia Sinigaglia, Bruno Sá, Nils Wistoff, Yvan Tortorella, Simone Benatti, Rafail Psiakis, Ari Kulmala, Baker Mohammad, Sandro Pinto, Daniele Palossi, Luca Benini, Davide Rossi
2024 J jnl
A Heterogeneous RISC-V based SoC for Secure Nano-UAV Navigation.
CoRR
Luca Valente, Alessandro Nadalini, Asif Veeran, Mattia Sinigaglia, Bruno Sá, Nils Wistoff, Yvan Tortorella, Simone Benatti, Rafail Psiakis, Ari Kulmala, Baker Mohammad, Sandro Pinto, Daniele Palossi, Luca Benini, Davide Rossi
2024 J jnl
Culsans: An Efficient Snoop-based Coherency Unit for the CVA6 Open Source RISC-V application processor.
CoRR
Riccardo Tedeschi, Luca Valente, Gianmarco Ottavi, Enrico Zelioli, Nils Wistoff, Massimiliano Giacometti, Abdul Basit Sajjad, Luca Benini, Davide Rossi
2024 J jnl
Culsans: An Efficient Snoop-based Coherency Unit for the CVA6 Open Source RISC-V application processor.
WiPiEC Journal
Riccardo Tedeschi, Luca Valente, Gianmarco Ottavi, Enrico Zelioli, Nils Wistoff, Massimiliano Giacometti, Abdul Basit Sajjad, Luca Benini, Davide Rossi
2024 — conf
Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-Based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET.
VLSI Technology and Circuits
Gianna Paulin, Paul Scheffler, Thomas Benz, Matheus A. Cavalcante, Tim Fischer, Manuel Eggimann, Yichao Zhang, Nils Wistoff, Luca Bertaccini, Luca Colagrande, Gianmarco Ottavi, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2024 J jnl
Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET.
CoRR
Gianna Paulin, Paul Scheffler, Thomas Benz, Matheus A. Cavalcante, Tim Fischer, Manuel Eggimann, Yichao Zhang, Nils Wistoff, Luca Bertaccini, Luca Colagrande, Gianmarco Ottavi, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2024 — conf
fence.t.s: Closing Timing Channels in High-Performance Out-of-Order Cores Through ISA-Supported Temporal Partitioning.
ApplePies
Nils Wistoff, Gernot Heiser, Luca Benini
2024 J jnl
fence.t.s: Closing Timing Channels in High-Performance Out-of-Order Cores through ISA-Supported Temporal Partitioning.
CoRR
Nils Wistoff, Gernot Heiser, Luca Benini
2024 C conf
vCLIC: Towards Fast Interrupt Handling in Virtualized RISC-V Mixed-Criticality Systems.
ICCD
Enrico Zelioli, Alessandro Ottaviano, Robert Balas, Nils Wistoff, Angelo Garofalo, Luca Benini
2024 J jnl
vCLIC: Towards Fast Interrupt Handling in Virtualized RISC-V Mixed-criticality Systems.
CoRR
Enrico Zelioli, Alessandro Ottaviano, Robert Balas, Nils Wistoff, Angelo Garofalo, Luca Benini
2023 A* conf
AutoCC: Automatic Discovery of Covert Channels in Time-Shared Hardware.
MICRO
Marcelo Orenes-Vera, Hyunsung Yun, Nils Wistoff, Gernot Heiser, Luca Benini, David Wentzlaff, Margaret Martonosi
2023 J jnl
Proving the Absence of Microarchitectural Timing Channels.
CoRR
Scott Buckley, Robert Sison, Nils Wistoff, Curtis Millar, Toby Murray, Gerwin Klein, Gernot Heiser
2023 — conf
Shaheen: An Open, Secure, and Scalable RV64 SoC for Autonomous Nano-UAVs.
HCS
Luca Valente, Asif Veeran, Mattia Sinigaglia, Yvan Tortorella, Alessandro Nadalini, Nils Wistoff, Bruno Sá, Angelo Garofalo, Rafail Psiakis, M. Tolba, Ari Kulmala, Nimisha Limaye, Ozgur Sinanoglu, Sandro Pinto, Daniele Palossi, Luca Benini, Baker Mohammad, Davide Rossi
2023 J jnl
Systematic Prevention of On-Core Timing Channels by Full Temporal Partitioning.
IEEE Trans. Computers
Nils Wistoff, Moritz Schneider, Frank K. Gürkaynak, Gernot Heiser, Luca Benini
2023 — conf
Towards a RISC-V Open Platform for Next-generation Automotive ECUs.
MECO
Luca Cuomo, Claudio Scordino, Alessandro Ottaviano, Nils Wistoff, Robert Balas, Luca Benini, Errico Guidieri, Ida Maria Savino
2023 J jnl
Towards a RISC-V Open Platform for Next-generation Automotive ECUs.
CoRR
Luca Cuomo, Claudio Scordino, Alessandro Ottaviano, Nils Wistoff, Robert Balas, Luca Benini, Errico Guidieri, Ida Maria Savino
2022 — conf
A "New Ara" for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design.
ASAP
Matteo Perotti, Matheus A. Cavalcante, Nils Wistoff, Renzo Andri, Lukas Cavigelli, Luca Benini
2022 J jnl
A "New Ara" for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design.
CoRR
Matteo Perotti, Matheus A. Cavalcante, Nils Wistoff, Renzo Andri, Lukas Cavigelli, Luca Benini
2022 — conf
On-Demand Redundancy Grouping: Selectable Soft-Error Tolerance for a Multicore Cluster.
ISVLSI
Michael Rogenmoser, Nils Wistoff, Pirmin Vogel, Frank K. Gürkaynak, Luca Benini
2022 J jnl
On-Demand Redundancy Grouping: Selectable Soft-Error Tolerance for a Multicore Cluster.
CoRR
Michael Rogenmoser, Nils Wistoff, Pirmin Vogel, Frank K. Gürkaynak, Luca Benini
2022 J jnl
Systematic Prevention of On-Core Timing Channels by Full Temporal Partitioning.
CoRR
Nils Wistoff, Moritz Schneider, Frank K. Gürkaynak, Gernot Heiser, Luca Benini
2021 A conf
Microarchitectural Timing Channels and their Prevention on an Open-Source 64-bit RISC-V Core.
DATE
Nils Wistoff, Moritz Schneider, Frank K. Gürkaynak, Luca Benini, Gernot Heiser
2020 J jnl
Prevention of Microarchitectural Covert Channels on an Open-Source 64-bit RISC-V Core.
CoRR
Nils Wistoff, Moritz Schneider, Frank K. Gürkaynak, Luca Benini, Gernot Heiser