Nilanjan Mukherjee

100 papers A* 3A 33B 3Misc 15Journal 32Unranked 14

Year	Rank	Type	Title / Venue / Authors
2025	A	`conf`	In-Field Testing using In-System Embedded Deterministic Test as a solution to alleviate Silent Data Corruption in AI designs. ITC Varun Sehgal, Subramanian Mahadevan, Ashrith S. Harith, Mohit Sharma, Saket Goyal, Nilanjan Mukherjee
2025	Misc	`conf`	Timing-Verification Test Generation Targeting Small Delay Defects. VTS Jiezhong Wu, Nilanjan Mukherjee, Irith Pomeranz, Kun-Han Tsai, Janusz Rajski
2024	A	`conf`	Delay Monitoring Under Different PVT Corners for Test and Functional Operation. ITC Hari Addepalli, Jiezhong Wu, Nilanjan Mukherjee, Irith Pomeranz, Janusz Rajski
2024	A	`conf`	Deterministic In-Fleet Scan Test for a Cloud Computing Platform. ITC Dan Trock, Subramanian Mahadevan, Nilanjan Mukherjee, Lee Harrison, Janusz Rajski, Jerzy Tyszer
2024	J	`jnl`	Generation of Two-Cycle Tests for Structurally Similar Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jerin Joe, Nilanjan Mukherjee, Irith Pomeranz, Janusz Rajski
2024	J	`jnl`	The Future of Design for Test and Silicon Lifecycle Management. IEEE Des. Test Janusz Rajski, Vivek Chickermane, Jean-François Côté, Stephan Eggersglüß, Nilanjan Mukherjee, Jerzy Tyszer
2024	Misc	`conf`	X-Tolerant Logic BIST for Automotive Designs using Observation Scan Technology. VLSID Ashrith S. Harith, Yingdi Liu, Nilanjan Mukherjee, Jeffrey Mayer
2023	Misc	`conf`	Innovation Practices Track: Silicon Lifecycle Management Challenges and Opportunities. VTS Fei Su, Xiankun Robert Jin, Nilanjan Mukherjee, Yervant Zorian
2022	Misc	`conf`	Fast Test Generation for Structurally Similar Circuits. VTS Jerin Joe, Nilanjan Mukherjee, Irith Pomeranz, Janusz Rajski
2022	J	`jnl`	LBIST for Automotive ICs With Enhanced Test Generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Bartosz Kaczmarek, Grzegorz Mrugalski, Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Lukasz Rybak, Jerzy Tyszer
2022	A	`conf`	Test Generation for an Iterative Design Flow with RTL Changes. ITC Jerin Joe, Nilanjan Mukherjee, Irith Pomeranz, Janusz Rajski
2021	—	`conf`	Automotive Test and Reliability. ITC-Asia Yu Huang, David Francis, Yervant Zorian, Nilanjan Mukherjee
2021	J	`jnl`	Time and Area Optimized Testing of Automotive ICs. IEEE Trans. Very Large Scale Integr. Syst. Nilanjan Mukherjee, Daniel Tille, Mahendar Sapati, Yingdi Liu, Jeffrey Mayer, Sylwester Milewski, Elham K. Moghaddam, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer
2021	J	`jnl`	X-Tolerant Compactor maXpress for In-System Test Applications With Observation Scan. IEEE Trans. Very Large Scale Integr. Syst. Yingdi Liu, Sylwester Milewski, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Bartosz Wlodarczak
2020	J	`jnl`	Deterministic Stellar BIST for Automotive ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yingdi Liu, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer
2020	Misc	`conf`	Effective Design of Layout-Friendly EDT Decompressor. VTS Yu Huang, Janusz Rajski, Mark Kassab, Nilanjan Mukherjee, Jeffrey Mayer
2020	B	`conf`	Test Sequence-Optimized BIST for Automotive Applications. ETS Bartosz Kaczmarek, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Lukasz Rybak, Jerzy Tyszer
2020	A	`conf`	X-Tolerant Tunable Compactor for In-System Test. ITC Yingdi Liu, Sylwester Milewski, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Bartosz Wldarczak
2019	J	`jnl`	Logic BIST With Capture-Per-Clock Hybrid Test Points. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Justyna Zawada
2019	A	`conf`	Test Time and Area Optimized BrST Scheme for Automotive ICs. ITC Nilanjan Mukherjee, Jerzy Tyszer, Daniel Tille, Mahendar Sapati, Yingdi Liu, Jeffrey Mayer, Sylwester Milewski, Elham K. Moghaddam, Janusz Rajski, Jedrzej Solecki
2018	A	`conf`	Deterministic Stellar BIST for In-System Automotive Test. ITC Yingdi Liu, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer
2018	J	`jnl`	Hardware Protection via Logic Locking Test Points. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Michael Chen, Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Justyna Zawada
2017	J	`jnl`	Embedded Deterministic Test Points. IEEE Trans. Very Large Scale Integr. Syst. Cesar Acero, Derek Feltham, Yingdi Liu, Elham K. Moghaddam, Nilanjan Mukherjee, Marek Patyra, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Justyna Zawada
2017	A	`conf`	Full-scan LBIST with capture-per-cycle hybrid test points. ITC Sylwester Milewski, Nilanjan Mukherjee, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Justyna Zawada
2016	Misc	`conf`	Digital Testing of ICs for Automotive Applications. VLSID Nilanjan Mukherjee, Janusz Rajski
2016	A	`conf`	Minimal area test points for deterministic patterns. ITC Yingdi Liu, Elham K. Moghaddam, Nilanjan Mukherjee, Sudhakar M. Reddy, Janusz Rajski, Jerzy Tyszer
2016	J	`jnl`	On New Test Points for Compact Cell-Aware Tests. IEEE Des. Test Cesar Acero, Derek Feltham, Marek Patyra, Friedrich Hapke, Elham K. Moghaddam, Nilanjan Mukherjee, Vidya Neerkundar, Janusz Rajski, Jerzy Tyszer, Justyna Zawada
2016	—	`conf`	On Test Points Enhancing Hardware Security. ATS Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Justyna Zawada
2016	A	`conf`	Test point insertion in hybrid test compression/LBIST architectures. ITC Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Justyna Zawada
2015	A*	`conf`	Design for low test pattern counts. DAC Haluk Konuk, Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Deepak Solanki, Jerzy Tyszer, Justyna Zawada
2015	A	`conf`	Embedded deterministic test points for compact cell-aware tests. ITC Cesar Acero, Derek Feltham, Friedrich Hapke, Elham K. Moghaddam, Nilanjan Mukherjee, Vidya Neerkundar, Marek Patyra, Janusz Rajski, Jerzy Tyszer, Justyna Zawada
2015	Misc	`conf`	Innovative practices session 11C: Advanced scan methodologies [3 presentations]. VTS Janusz Rajski, Nilanjan Mukherjee
2015	J	`jnl`	Isometric Test Data Compression. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Amit Kumar, Mark Kassab, Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Chen Wang
2015	J	`jnl`	Low-Power Programmable PRPG With Test Compression Capabilities. IEEE Trans. Very Large Scale Integr. Syst. Michal Filipek, Grzegorz Mrugalski, Nilanjan Mukherjee, Benoit Nadeau-Dostie, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer
2015	J	`jnl`	Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures. IEEE Trans. Very Large Scale Integr. Syst. Wu-Tung Cheng, Yan Dong, Grady Giles, Yu Huang, Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
2014	J	`jnl`	Erratum to "Test Time Reduction in EDT Bandwidth Management for SoC Designs". IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
2014	—	`conf`	High-Speed Serial Embedded Deterministic Test for System-on-Chip Designs. ATS Maciej Trawka, Grzegorz Mrugalski, Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jakub Janicki, Jerzy Tyszer
2014	Misc	`conf`	Innovative practices session 1C: Existing/emerging low power techniques. VTS Charutosh Dixit, Ramesh C. Tekumalla, Wei Zhao, Nilanjan Mukherjee, Vivek Chickermane
2014	A	`conf`	Isometric test compression with low toggling activity. ITC Amit Kumar, Mark Kassab, Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Chen Wang
2014	A*	`conf`	On Using Implied Values in EDT-based Test Compression. DAC Marcin Gebala, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
2013	A	`conf`	EDT bandwidth management - Practical scenarios for large SoC designs. ITC Jakub Janicki, Jerzy Tyszer, Wu-Tung Cheng, Yu Huang, Mark Kassab, Nilanjan Mukherjee, Janusz Rajski, Yan Dong, Grady Giles
2013	B	`conf`	New test compression scheme based on low power BIST. ETS Jerzy Tyszer, Michal Filipek, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski
2013	J	`jnl`	On Deploying Scan Chains for Data Storage in Test Compression Environment. IEEE Des. Test Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
2013	J	`jnl`	Test Time Reduction in EDT Bandwidth Management for SoC Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
2012	J	`jnl`	EDT Bandwidth Management in SoC Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
2012	A	`conf`	Low power programmable PRPG with enhanced fault coverage gradient. ITC Jedrzej Solecki, Jerzy Tyszer, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski
2011	J	`jnl`	BIST-Based Fault Diagnosis for Read-Only Memories. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer
2011	J	`jnl`	Deterministic Clustering of Incompatible Test Cubes for Higher Power-Aware EDT Compression. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Przemyslaw Szczerbicki, Jerzy Tyszer
2011	A	`conf`	EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism. ITC Jakub Janicki, Jerzy Tyszer, Avijit Dutta, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski
2011	—	`conf`	Fault Diagnosis in Memory BIST Environment with Non-march Tests. Asian Test Symposium Grzegorz Mrugalski, Artur Pogiel, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Pawel Urbanek
2011	—	`conf`	Power Aware Embedded Test. Asian Test Symposium Xijiang Lin, Elham K. Moghaddam, Nilanjan Mukherjee, Benoit Nadeau-Dostie, Janusz Rajski, Jerzy Tyszer
2011	B	`conf`	Reduced ATE Interface for High Test Data Compression. ETS Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
2011	J	`jnl`	Ring Generator: An Ultimate Linear Feedback Shift Register. Computer Nilanjan Mukherjee, Janusz Rajski, Grzegorz Mrugalski, Artur Pogiel, Jerzy Tyszer
2010	A	`conf`	Dynamic channel allocation for higher EDT compression in SoC designs. ITC Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jakub Janicki, Jerzy Tyszer
2010	J	`jnl`	High Volume Diagnosis in Memory BIST Based on Compressed Failure Data. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer
2010	A	`conf`	Low capture power at-speed test in EDT environment. ITC Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Xijiang Lin, Nilanjan Mukherjee, Mark Kassab
2010	A	`conf`	Low power compression of incompatible test cubes. ITC Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Przemyslaw Szczerbicki, Jerzy Tyszer
2010	J	`jnl`	On Compaction Utilizing Inter and Intra-Correlation of Unknown States. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
2009	A	`conf`	Compression based on deterministic vector clustering of incompatible test cubes. ITC Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Dariusz Czysz, Jerzy Tyszer
2009	Misc	`conf`	Defect Aware to Power Conscious Tests - The New DFT Landscape. VLSI Design Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
2009	A	`conf`	Fault diagnosis for embedded read-only memories. ITC Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer
2009	Misc	`conf`	High-Speed On-Chip Event Counters for Embedded Systems. VLSI Design Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer
2009	Misc	`conf`	Highly X-Tolerant Selective Compaction of Test Responses. VTS Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Dariusz Czysz, Jerzy Tyszer
2008	A	`conf`	High Test Quality in Low Pin Count Applications. ITC Jayant D'Souza, Subramanian Mahadevan, Nilanjan Mukherjee, Graham Rhodes, Jocelyn Moreau, Thomas Droniou, Paul Armagnat, Damien Sartoretti
2008	A	`conf`	High Throughput Diagnosis via Compression of Failure Data in Embedded Memory BIST. ITC Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer
2008	—	`conf`	Targeting "Zero DPPM" - Can we ever get there? DFT Nilanjan Mukherjee
2008	J	`jnl`	X-Press: Two-Stage X-Tolerant Compactor With Programmable Selector. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Wu-Tung Cheng, Nilanjan Mukherjee, Mark Kassab
2007	—	`conf`	A RTL Testability Analyzer Based on Logical Virtual Prototyping. ATS Yu Huang, Nilanjan Mukherjee, Wu-Tung Cheng, Greg Aldrich
2007	J	`jnl`	X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis. IEEE Des. Test Comput. Jerzy Tyszer, Janusz Rajski, Grzegorz Mrugalski, Nilanjan Mukherjee, Mark Kassab, Wu-Tung Cheng, Manish Sharma, Liyang Lai
2006	—	`conf`	A Field Programmable Memory BIST Architecture Supporting Algorithms with Multiple Nested Loops. ATS Xiaogang Du, Nilanjan Mukherjee, Chris Hill, Wu-Tung Cheng, Sudhakar M. Reddy
2006	J	`jnl`	High Performance Dense Ring Generators. IEEE Trans. Computers Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
2006	A	`conf`	X-Press Compactor for 1000x Reduction of Test Data. ITC Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Wu-Tung Cheng, Nilanjan Mukherjee, Mark Kassab
2005	—	`conf`	Achieving High Test Quality with Reduced Pin Count Testing. Asian Test Symposium Jay Jahangiri, Nilanjan Mukherjee, Wu-Tung Cheng, Subramanian Mahadevan, Ron Press
2005	A	`conf`	Chasing subtle embedded RAM defects for nanometer technologies. ITC Theo J. Powell, Amrendra Kumar, Joseph Rayhawk, Nilanjan Mukherjee
2005	—	`conf`	Full-speed field programmable memory BIST supporting multi-level looping. MTDT Xiaogang Du, Nilanjan Mukherjee, Wu-Tung Cheng, Sudhakar M. Reddy
2005	A	`conf`	Full-speed field-programmable memory BIST architecture. ITC Xiaogang Du, Nilanjan Mukherjee, Wu-Tung Cheng, Sudhakar M. Reddy
2005	—	`conf`	Improving Test Quality Using Test Data Compression. Asian Test Symposium Nilanjan Mukherjee
2004	Misc	`conf`	At-Speed Built-in Self-Repair Analyzer for Embedded Word-Oriented Memories. VLSI Design Xiaogang Du, Sudhakar M. Reddy, Wu-Tung Cheng, Joseph Rayhawk, Nilanjan Mukherjee
2004	A	`conf`	Cost of Test - Taking Control. ITC Nilanjan Mukherjee
2004	Misc	`conf`	Embedded Test for Low Cost Manufacturing. VLSI Design Janusz Rajski, Nilanjan Mukherjee, Jerzy Tyszer, Thomas Rinderknecht
2004	J	`jnl`	Embedded deterministic test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee
2004	Misc	`conf`	Planar High Performance Ring Generators. VTS Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
2003	J	`jnl`	Embedded Deterministic Test for Low-Cost Manufacturing. IEEE Des. Test Comput. Janusz Rajski, Mark Kassab, Nilanjan Mukherjee, Nagesh Tamarapalli, Jerzy Tyszer, Jun Qian
2003	A	`conf`	Industrial Experience with Adoption of EDT for Low-Cost Test without Concessions. ITC Frank Poehl, Matthias Beck, Ralf Arnold, Peter Muhmenthaler, Nagesh Tamarapalli, Mark Kassab, Nilanjan Mukherjee, Janusz Rajski
2003	—	`conf`	Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets. ISQED Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Sudhakar M. Reddy
2002	—	`conf`	Constraint Driven Pin Mapping for Concurrent SOC Testing. ASP-DAC/VLSI Design Yu Huang, Nilanjan Mukherjee, Chien-Chung Tsai, Omer Samman, Yahya Zaidan, Yanping Zhang, Wu-Tung Cheng, Sudhakar M. Reddy
2002	A	`conf`	Embedded Deterministic Test for Low-Cost Manufacturing Test. ITC Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee, Rob Thompson, Kun-Han Tsai, Andre Hertwig, Nagesh Tamarapalli, Grzegorz Mrugalski, Geir Eide, Jun Qian
2002	J	`jnl`	On Concurrent Test of Core-Based SOC Design. J. Electron. Test. Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Yahya Zaidan, Sudhakar M. Reddy
2002	A	`conf`	Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm. ITC Yu Huang, Sudhakar M. Reddy, Wu-Tung Cheng, Paul Reuter, Nilanjan Mukherjee, Chien-Chung Tsai, Omer Samman, Yahya Zaidan
2002	J	`jnl`	Synthesis of Scan Chains for Netlist Descriptions at RT-Level. J. Electron. Test. Yu Huang, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Wu-Tung Cheng, Sudhakar M. Reddy
2001	A	`conf`	On RTL scan design. ITC Yu Huang, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Dan Devries, Wu-Tung Cheng, Sudhakar M. Reddy
2001	—	`conf`	Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC D. Asian Test Symposium Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Yahya Zaidan, Sudhakar M. Reddy
2001	J	`jnl`	Testing Schemes for FIR Filter Structures. IEEE Trans. Computers Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
1999	J	`jnl`	Built in self test: a complete test solution for telecommunication systems. IEEE Commun. Mag. Nilanjan Mukherjee, Tapan J. Chakraborty, Ramesh Karri
1998	A	`conf`	A BIST scheme for the detection of path-delay faults. ITC Nilanjan Mukherjee, Tapan J. Chakraborty, Sudipta Bhawmik
1997	J	`jnl`	Design of Testable Multipliers for Fixed-Width Data Paths. IEEE Trans. Computers Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
1997	A	`conf`	Parameterizable Testing Scheme for FIR Filters. ITC Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
1995	Misc	`conf`	Arithmetic built-in self test for high-level synthesis. VTS Nilanjan Mukherjee, H. Kassab, Janusz Rajski, Jerzy Tyszer
1995	A	`conf`	On testable multipliers for fixed-width data path architectures. ICCAD Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
1995	A*	`conf`	Software Accelerated Functional Fault Simulation for Data-Path Architectures. DAC Mark Kassab, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer