Nikolaos Vassiliadis

16 papers A 1C 1Journal 7Unranked 7
YearRankTypeTitle / Venue / Authors
2014 J jnl
Real-Time Machine Vision FPGA Implementation for Microfluidic Monitoring on Lab-on-Chips.
IEEE Trans. Biomed. Circuits Syst.
Calliope-Louisa Sotiropoulou, Liberis Voudouris, Christos Gentsos, Athanasios M. Demiris, Nikolaos Vassiliadis, Spiridon Nikolaidis
2012 C conf
FPGA-based machine vision implementation for Lab-on-Chip flow detection.
ISCAS
Calliope-Louisa Sotiropoulou, Liberis Voudouris, Christos Gentsos, Spiridon Nikolaidis, Nikolaos Vassiliadis, Athanasios M. Demiris, Spyros Blionas
2010 — conf
Real-time canny edge detection parallel implementation for FPGAs.
ICECS
Christos Gentsos, Calliope-Louisa Sotiropoulou, Spiridon Nikolaidis, Nikolaos Vassiliadis
2009 J jnl
An Application Development Framework for ARISE Reconfigurable Processors.
ACM Trans. Reconfigurable Technol. Syst.
Nikolaos Vassiliadis, George Theodoridis, Spiridon Nikolaidis
2009 J jnl
An integer linear programming model for mapping applications on hybrid systems.
IET Comput. Digit. Tech.
George Theodoridis, Nikolaos Vassiliadis, Spiridon Nikolaidis
2009 J jnl
The ARISE Approach for Extending Embedded Processors With Arbitrary Hardware Accelerators.
IEEE Trans. Very Large Scale Integr. Syst.
Nikolaos Vassiliadis, George Theodoridis, Spiridon Nikolaidis
2008 — conf
ARISE Machines: Extending Processors with Hybrid Accelerators.
ARC
Nikolaos Vassiliadis, George Theodoridis, Spiridon Nikolaidis
2007 — conf
The ARISE Reconfigurable Instruction Set Extensions Framework.
ICSAMOS
Nikolaos Vassiliadis, George Theodoridis, Spiridon Nikolaidis
2006 A conf
An automated development framework for a RISC processor with reconfigurable instruction set extensions.
IPDPS
Nikolaos Vassiliadis, George Theodoridis, Spiridon Nikolaidis
2006 — conf
Enhancing a Reconfigurable Instruction Set Processor with Partial Predication and Virtual Opcode Support.
ARC
Nikolaos Vassiliadis, George Theodoridis, Spiridon Nikolaidis
2005 J jnl
A Novel FPGA Architecture and an Integrated Framework of CAD Tools for Implementing Applications.
IEICE Trans. Inf. Syst.
Kostas Siozios, George Koutroumpezis, Konstantinos Tatas, Nikolaos Vassiliadis, Vasilios Kalenteridis, Haroula Pournara, Ilias Pappas, Dimitrios Soudris, Antonios Thanailakis, Spiridon Nikolaidis, Stilianos Siskos
2005 J jnl
A complete platform and toolset for system implementation on fine-grain reconfigurable hardware.
Microprocess. Microsystems
Vasilios Kalenteridis, Haroula Pournara, Kostas Siozios, Konstantinos Tatas, Nikolaos Vassiliadis, Ilias Pappas, George Koutroumpezis, Spiridon Nikolaidis, Stilianos Siskos, D. J. Soudris
2005 — conf
AMDREL: a novel low-energy FPGA architecture and supporting CAD tool design flow.
ASP-DAC
Dimitrios Soudris, Spiridon Nikolaidis, Stilianos Siskos, Konstantinos Tatas, Kostas Siozios, George Koutroumpezis, Nikolaos Vassiliadis, Vasilios Kalenteridis, Haroula Pournara, Ilias Pappas, Adonios Thanailakis
2005 J jnl
The effect of Data-Reuse Transformations on Multimedia Applications for Application Specific Processors.
Int. J. Comput.
Nikolaos Vassiliadis, A. Chormoviti, Nikolaos Kavvadias, Spiridon Nikolaidis
2004 — conf
The Effect of Data-Reuse Transformations on Multimedia Applications for Different Processing Platforms.
PATMOS
Nikolaos Vassiliadis, A. Chormoviti, Nikolaos Kavvadias, Spiridon Nikolaidis
2003 — conf
FPGA Architecture Design and Toolset for Logic Implementation.
PATMOS
Konstantinos Tatas, Kostas Siozios, Nikolaos Vassiliadis, D. J. Soudris, Spiridon Nikolaidis, Stilianos Siskos, Adonios Thanailakis