Nikola Nedovic

30 papers A* 1A 1C 2Journal 9Unranked 17

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	A 32 Gb/s/λ 256Gb/S/Fiber Half-Rate Bandpass-Filtered Clock-Forwarding DWDM Optical Link in a 3D-Stacked 7nm EIC/65nm PIC Technology. ISSCC Sanquan Song, Nandish Mehta, Nikola Nedovic, Angad Rekhi, Georgios Kalogerakis, Li Xu, Brian Zimmer, Stephen G. Tell, Yoshinori Nishi, Xi Chen, Ward Lopes, Benjamin G. Lee, Thomas H. Greer, C. Thomas Gray
2024	—	`conf`	16.4 High-Density and Low-Power PUF Designs in 5nm Achieving 23× and 39× BER Reduction After Unstable Bit Detection and Masking. ISSCC Sudhir S. Kudva, Mahmut Ersin Sinangil, Stephen G. Tell, Nikola Nedovic, Sanquan Song, Brian Zimmer, C. Thomas Gray
2024	J	`jnl`	A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS. IEEE J. Solid State Circuits Yoshinori Nishi, John W. Poulton, Walker J. Turner, Xi Chen, Sanquan Song, Brian Zimmer, Stephen G. Tell, Nikola Nedovic, John M. Wilson, William J. Dally, C. Thomas Gray
2023	—	`conf`	A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS. VLSI Technology and Circuits Yoshinori Nishi, John W. Poulton, Xi Chen, Sanquan Song, Brian Zimmer, Walker J. Turner, Stephen G. Tell, Nikola Nedovic, John M. Wilson, William J. Dally, C. Thomas Gray
2023	J	`jnl`	A 0.297-pJ/Bit 50.4-Gb/s/Wire Inverter-Based Short-Reach Simultaneous Bi-Directional Transceiver for Die-to-Die Interface in 5-nm CMOS. IEEE J. Solid State Circuits Yoshinori Nishi, John W. Poulton, Walker J. Turner, Xi Chen, Sanquan Song, Brian Zimmer, Stephen G. Tell, Nikola Nedovic, John M. Wilson, William J. Dally, C. Thomas Gray
2022	—	`conf`	A 0.297-pJ/bit 50.4-Gb/s/wire Inverter-Based Short-Reach Simultaneous Bidirectional Transceiver for Die-to-Die Interface in 5nm CMOS. VLSI Technology and Circuits Yoshinori Nishi, John W. Poulton, Xi Chen, Sanquan Song, Brian Zimmer, Walker J. Turner, Stephen G. Tell, Nikola Nedovic, John M. Wilson, William J. Dally, C. Thomas Gray
2022	—	`conf`	An FLL-Based Clock Glitch Detector for Security Circuits in a 5nm FINFET Process. VLSI Technology and Circuits Sanquan Song, Stephen G. Tell, Brian Zimmer, Sudhir S. Kudva, Nikola Nedovic, C. Thomas Gray
2020	—	`conf`	6.6 Reference-Noise Compensation Scheme for Single-Ended Package-to-Package Links. ISSCC Xi Chen, Nikola Nedovic, Stephen G. Tell, Sudhir S. Kudva, Brian Zimmer, Thomas H. Greer, John W. Poulton, Sanquan Song, Walker J. Turner, John M. Wilson, C. Thomas Gray
2019	J	`jnl`	A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator. IEEE J. Solid State Circuits John W. Poulton, John M. Wilson, Walker J. Turner, Brian Zimmer, Xi Chen, Sudhir S. Kudva, Sanquan Song, Stephen G. Tell, Nikola Nedovic, Wenxu Zhao, Sunil R. Sudhakaran, C. Thomas Gray, William J. Dally
2019	—	`conf`	A 2-to-20 GHz Multi-Phase Clock Generator with Phase Interpolators Using Injection-Locked Oscillation Buffers for High-Speed IOs in 16nm FinFET. CICC Sanquan Song, John Poulton, Xi Chen, Brian Zimmer, Stephen G. Tell, Walker J. Turner, Sudhir S. Kudva, Nikola Nedovic, John M. Wilson, C. Thomas Gray, William J. Dally
2019	A*	`conf`	Analog/Mixed-Signal Hardware Error Modeling for Deep Learning Inference. DAC Angad S. Rekhi, Brian Zimmer, Nikola Nedovic, Ningxi Liu, Rangharajan Venkatesan, Miaorong Wang, Brucek Khailany, William J. Dally, C. Thomas Gray
2019	—	`conf`	Voltage-Follower Coupling Quadrature Oscillator with Embedded Phase-Interpolator in 16nm FinFET. CICC Xi Chen, Sanquan Song, John Poulton, Nikola Nedovic, Brian Zimmer, Stephen G. Tell, C. Thomas Gray
2018	—	`conf`	A 1.17pJ/b 25Gb/s/pin ground-referenced single-ended serial link for off- and on-package communication in 16nm CMOS using a process- and temperature-adaptive voltage regulator. ISSCC John M. Wilson, Walker J. Turner, John W. Poulton, Brian Zimmer, Xi Chen, Sudhir S. Kudva, Sanquan Song, Stephen G. Tell, Nikola Nedovic, Wenxu Zhao, Sunil R. Sudhakaran, C. Thomas Gray, William J. Dally
2018	—	`conf`	Ground-referenced signaling for intra-chip and short-reach chip-to-chip interconnects. CICC Walker J. Turner, John W. Poulton, John M. Wilson, Xi Chen, Stephen G. Tell, Matthew Fojtik, Thomas H. Greer, Brian Zimmer, Sanquan Song, Nikola Nedovic, Sudhir S. Kudva, Sunil R. Sudhakaran, Rizwan Bashirullah, Wenxu Zhao, William J. Dally, C. Thomas Gray
2014	—	`conf`	A DC-46Gb/s 2: 1 multiplexer and source-series terminated driver in 20nm CMOS technology. A-SSCC Jian Hong Jiang, Samir Parikh, Mark Lionbarger, Nikola Nedovic, Takuji Yamamoto
2010	J	`jnl`	A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS. IEEE J. Solid State Circuits Nikola Nedovic, Anders Kristensson, Samir Parikh, Subodh M. Reddy, Scott McLeod, Nestoras Tzartzanis, Kouichi Kanda, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Takayuki Shibasaki, Yasumoto Tomita, Takayuki Hamada, Mariko Sugawara, Tadashi Ikeuchi, Naoki Kuwata, Hirotaka Tamura, Junji Ogawa, William W. Walker
2008	J	`jnl`	Jitter Analysis of Nonautonomous MOS Current-Mode Logic Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. Marko Aleksic, Nikola Nedovic, K. Wayne Current, Vojin G. Oklobdzija
2007	J	`jnl`	A 40-44 Gb/s 3 × Oversampling CMOS CDR/1: 16 DEMUX. IEEE J. Solid State Circuits Nikola Nedovic, Nestoras Tzartzanis, Hirotaka Tamura, Francis M. Rotella, Magnus Wiklund, Yuma Mizutani, Yusuke Okaniwa, Tadahiro Kuroda, Junji Ogawa, William W. Walker
2007	—	`conf`	A 40-to-44Gb/s 3�? Oversampling CMOS CDR/1: 16 DEMUX. ISSCC Nikola Nedovic, Nestoras Tzartzanis, Hirotaka Tamura, Francis M. Rotella, Magnus Wiklund, Yuma Mizutani, Yusuke Okaniwa, Tadahiro Kuroda, Junji Ogawa, William W. Walker
2007	J	`jnl`	The Effect of the System Specification on the Optimal Selection of Clocked Storage Elements. IEEE J. Solid State Circuits Christophe Giacomotto, Nikola Nedovic, Vojin G. Oklobdzija
2006	—	`conf`	Energy-Delay Space Analysis for Clocked Storage Elements Under Process Variations. PATMOS Christophe Giacomotto, Nikola Nedovic, Vojin G. Oklobdzija
2005	—	`conf`	A New Model for Timing Jitter Caused by Device Noise in Current-Mode Logic Frequency Dividers. PATMOS Marko Aleksic, Nikola Nedovic, K. Wayne Current, Vojin G. Oklobdzija
2005	J	`jnl`	Dual-edge triggered storage elements and clocking strategy for low-power systems. IEEE Trans. Very Large Scale Integr. Syst. Nikola Nedovic, Vojin G. Oklobdzija
2004	J	`jnl`	A test circuit for measurement of clocked storage element characteristics. IEEE J. Solid State Circuits Nikola Nedovic, William W. Walker, Vojin G. Oklobdzija
2002	—	`conf`	Comparative analysis of double-edge versus single-edge triggered clocked storage elements. ISCAS (5) Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija
2002	A	`conf`	Conditional pre-charge techniques for power-efficient dual-edge clocking. ISLPED Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija
2001	—	`conf`	Conditional techniques for low power consumption flip-flops. ICECS Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija
2001	C	`conf`	Timing Characterization of Dual-edge Triggered Flip-flops. ICCD Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija
2000	C	`conf`	Dynamic Flip-Flop with Improved Power. ICCD Nikola Nedovic, Vojin G. Oklobdzija
2000	—	`conf`	Hybrid latch Flip-Flop with Improved Power Efficiency. SBCCI Nikola Nedovic, Vojin G. Oklobdzija