Nijwm Wary

26 papers C 8Misc 3Journal 10Unranked 5
YearRankTypeTitle / Venue / Authors
2025 J jnl
A 0.0375-pJ/bit Charge-Steering Based Hybrid for 8-Gb/s/pin Full-Duplex Chip-to-Chip Interconnects in 65-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap.
Prema Kumar Govindaswamy, Nijwm Wary, Vijay Shankar Pasupureddi
2025 C conf
A Hybrid SST-CML Full Duplex Simultaneous Bi-Directional Signaling Link.
ISCAS
Sree Kumar R. G., V. K. Surya, Nijwm Wary, Bibhu Datta Sahoo
2025 C conf
A Replica Driverless Common/Differential Mode Hybrid for Full-Duplex Signaling in Serial Links.
ISCAS
Pankaj Kumar, V. K. Surya, Sree Kumar R. G., Bibhu Datta Sahoo, Nijwm Wary
2025 C conf
Energy Efficient Voltage-Mode Simultaneous Bidirectional Transceiver for Serial Links.
ISCAS
Ankit Yadav, V. K. Surya, Sree Kumar R. G., Bibhu Datta Sahoo, Nijwm Wary
2025 Misc conf
Pin Efficient Tri-Level Based Inductive Coupling Transceiver for 3D ICs.
VLSID
Soumojit Bakshi, V. K. Surya, Nijwm Wary
2024 J jnl
Energy Efficient Integrated Summer and Latch-Based DFE With Reduced Tap Loading.
IEEE Trans. Circuits Syst. II Express Briefs
Suraj Kumar Prusty, V. K. Surya, Nijwm Wary
2024 J jnl
Energy Efficient Resistor-Transconductor Hybrid-Based Full-Duplex Transceiver for Serial Link.
IEEE Trans. Circuits Syst. I Regul. Pap.
V. K. Surya, Suraj Kumar Prusty, Bibhu Datta Sahoo, Nijwm Wary
2024 — conf
Machine Learning based Adaptation for CTLE of Serial Links.
APCCAS
Sujal Reddy Kariveda, Suraj Kumar Prusty, Nijwm Wary
2024 Misc conf
Use of current-mode and voltage-mode receivers together for on-chip multipoint-to-multipoint data transmission across global interconnects.
VLSID
Jahnvi Singh, Nijwm Wary, Pradip Mandal
2023 C conf
A 26 Gb/s Echo-Cancellation Based Simultaneous Bidirectional Transceiver in 65 nm CMOS.
ISCAS
V. K. Surya, Suraj Kumar Prusty, Nijwm Wary
2023 — conf
A Fully Integrated SCC DC-DC Converter with Novel FMC Controller for Fast Transient Response.
NEWCAS
Sahil Dalvi, Pilli Kalyan Kumar, Olive Ray, Nijwm Wary
2023 — conf
A High-Speed Charge-Injection based Double Tail Latch for Decision Feedback Equalizer (DFE).
NEWCAS
Suraj Kumar Prusty, V. K. Surya, Nijwm Wary
2022 C conf
A Low-Power Half-Rate Charge-Steering Hybrid for Full-Duplex Chip-to-Chip Interconnects.
ISCAS
Prema Kumar Govindaswamy, Nijwm Wary, Vijaya Sankara Rao Pasupureddi
2022 J jnl
Current-integrating summer for DFE receiver with low common mode variation.
Microelectron. J.
Poorna Chandrika Kondeti, Suraj Kumar Prusty, Nijwm Wary
2022 — conf
Design and Analysis of PVT Invariant Current Reference in 65-nm CMOS.
MWSCAS
Nishant Maurya, Nijwm Wary
2022 C conf
Power Efficient Echo-Cancellation Based Hybrid for Full-Duplex Chip-to-Chip Interconnects.
ISCAS
Prema Kumar Govindaswamy, Nijwm Wary, Vijaya Sankara Rao Pasupureddi
2021 J jnl
A Study of Discrete Multitone Modulation for Wireline Links Beyond 100 Gb/s.
IEEE Open J. Circuits Syst.
Behraz Vatankhahghadim, Nijwm Wary, James Bailey, Anthony Chan Carusone
2021 J jnl
A Study on Some Properties of Neutrosophic Multi Topological Group.
Symmetry
Bhimraj Basumatary, Nijwm Wary, Dimacha Dwibrang Mwchahary, Ashoke Kumar Brahma, Jwngsar Moshahary, Usha Rani Basumatary, Jili Basumatary
2020 C conf
All-Digital Calibration Algorithms to Correct for Static Non-Linearities in ADCs.
ISCAS
Paul Wenbo Chen, Nijwm Wary, Luke Wang, QiWei Wang, Anthony Chan Carusone
2020 C conf
Discrete Multitone Signalling for Wireline Communication.
ISCAS
Behraz Vatankhahghadim, Nijwm Wary, Anthony Chan Carusone
2020 J jnl
Hybrid bidirectional transceiver for multipoint-to-multipoint signalling across on-chip global interconnects.
IET Circuits Devices Syst.
Nijwm Wary, Antroy Roy Chowdhury, Pradip Mandal
2019 — conf
A Regulated-Cascode Based Current-Integrating TIA RX with 1-tap Speculative Adaptive DFE.
MWSCAS
Antroy Roy Chowdhury, Nijwm Wary, Pradip Mandal
2019 Misc conf
Energy Efficient Bidirectional Equalized Transceiver with PVT Insensitive Active Termination.
VLSID
Antroy Roy Chowdhury, Nijwm Wary, Pradip Mandal
2017 J jnl
Current-Mode Full-Duplex Transceiver for Lossy On-Chip Global Interconnects.
IEEE J. Solid State Circuits
Nijwm Wary, Pradip Mandal
2017 J jnl
Current-Mode Triline Transceiver for Coded Differential Signaling Across On-Chip Global Interconnects.
IEEE Trans. Very Large Scale Integr. Syst.
Nijwm Wary, Pradip Mandal
2015 J jnl
High-speed energy-efficient bi-directional transceiver for on-chip global interconnects.
IET Circuits Devices Syst.
Nijwm Wary, Pradip Mandal