Nihar Ranjan Mohapatra

17 papers C 1Misc 6Journal 3Unranked 7
YearRankTypeTitle / Venue / Authors
2025 Misc conf
Reliable High-Performance Programmable Voltage Regulator with 0.55A Sink Current for Cryo-Cooler Electronics in 0.18μm HV-CMOS Technology.
VLSID
Nishant Kumar, Hari Shanker Gupta, Nihar Ranjan Mohapatra
2024 C conf
A Programmable and Adaptive Dead-Time Controller for Low-Offset Output Generation for Cryo-Cooler Drive Applications.
ISCAS
Nishant Kumar, Hari Shanker Gupta, Anuj Srivastava, Nihar Ranjan Mohapatra
2024 Misc conf
K-means Clustering with ANN based Classification to Predict Current-Voltage Characteristics of Advanced FETs.
VLSID
Om Maheshwari, Dev Vyas, Nihar Ranjan Mohapatra
2023 J jnl
Process Voltage Temperature Variability Estimation of Tunneling Current for Band-to-Band-Tunneling based Neuron.
CoRR
Shubham Patil, Anand Sharma, Gaurav R, Abhishek Kadam, Ajay Kumar Singh, Sandip Lashkare, Nihar Ranjan Mohapatra, Udayan Ganguly
2023 — conf
Sub-nanosecond Delay High Voltage Level Shifter in 0.18μm HV-CMOS Technology for Cryo-Cooler Electronics.
APCCAS
Nishant Kumar, Hari Shanker Gupta, Nilesh M. Desai, Nihar Ranjan Mohapatra
2022 J jnl
Dispersion in Placement: Quantification and Insights.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Satyajit Mohapatra, Nihar Ranjan Mohapatra
2022 — conf
High Resolution Temperature Sensor Signal Processing ASIC for Cryo-Cooler Electronics.
VDAT
Anuj Srivastava, Nishant Kumar, Nihar Ranjan Mohapatra, Hari Shankar Gupta
2021 — conf
Behavior of LDMOS transistors at cryogenic temperature - An experiment based analysis.
VDAT
Kaushal Kumari Neeraj, Nihar Ranjan Mohapatra
2020 J jnl
Gradient Error Compensation in SC-MDACs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Satyajit Mohapatra, Nihar Ranjan Mohapatra
2020 Misc conf
The Design of Ultra Low Power SAR ADC for Implantable Cardioverter Defibrillator (ICD).
VLSID
Satyajit Mohapatra, Nihar Ranjan Mohapatra
2019 Misc conf
A Mismatch Resilient 16-Bit 20 MS/s Pipelined ADC.
VLSID
Satyajit Mohapatra, Hari Shanker Gupta, Nihar Ranjan Mohapatra, Sanjeev Mehta, Arup Roy Chowdhury, Nisha Pandya
2019 Misc conf
An Unified Charge Centroid Model for Silicon and Low Effective Mass III-V Channel Double Gate MOS Transistors.
VLSID
Amratansh Gupta, Mohit Ganeriwala, Nihar Ranjan Mohapatra
2019 — conf
Capacitance and Surface Potential Model for III-V Double-Gate FET.
ISDCS
Sarath Chandran G. M, Mohit D. Ganeriwala, Nihar Ranjan Mohapatra
2018 — conf
Mismatch Resilient 3.5-Bit MDAC with MCS-CFCS.
ISVLSI
Satyajit Mohapatra, Hari Shanker Gupta, Nihar Ranjan Mohapatra
2018 — conf
The HotSpot Compensation in High Speed Data Converters.
MWSCAS
Satyajit Mohapatra, Nihar Ranjan Mohapatra
2017 Misc conf
A 64b/66b Line Encoding for High Speed Serializers.
VLSID
Satyajit Mohapatra, Hari Shanker Gupta, Jatindeep Singh, Nihar Ranjan Mohapatra
2017 — conf
Performance Optimized 64b/66b Line Encoding Technique for High Speed SERDES Devices.
VDAT
Jatindeep Singh, Satyajit Mohapatra, Nihar Ranjan Mohapatra