Nihar R. Mohapatra

14 papers Misc 4Journal 5Unranked 5
YearRankTypeTitle / Venue / Authors
2026 J jnl
Inverse Design of High Power and High Voltage LDMOS Transistors Using Deep Learning-Based Sample-Efficient Surrogate Model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Rutu Patel, Ravi S. Hegde, Nihar R. Mohapatra
2025 J jnl
Exploring the impact of sheet thickness scaling on Nanosheet FET gate electrostatics using k.p based simulations.
Microelectron. J.
Ramandeep Kaur, Nihar R. Mohapatra
2024 J jnl
On the improved RF performance of step field plate LDMOS transistor.
Microelectron. J.
Rutu Patel, Nihar R. Mohapatra
2019 J jnl
Band-to-Band Tunneling based Ultra-Energy Efficient Silicon Neuron.
CoRR
Tanmay Chavan, Sangya Dutta, Nihar R. Mohapatra, Udayan Ganguly
2019 — conf
Design and Calibration of 14-bit 10 KS/s Low Power SAR ADC for Bio-medical Applications.
VDAT
Yadukrishnan Mekkattillam, Satyajit Mohapatra, Nihar R. Mohapatra
2018 — conf
An Ultra Energy Efficient Neuron enabled by Tunneling in Sub-threshold Regime on a Highly Manufacturable 32 nm SOI CMOS Technology.
DRC
Tanmay Chavan, S. Dutta, Nihar R. Mohapatra, Udayan Ganguly
2017 — conf
Low-Power Sequential Circuit Design Using Work-Function Engineered FinFETs.
VDAT
Ashish Soni, Abhijit Umap, Nihar R. Mohapatra
2017 — conf
Trap-assisted carrier transport through the multi-stack gate dielectrics of HKMG nMOS transistors: A compact model.
ESSDERC
Apoorva Ojha, Nihar R. Mohapatra
2016 Misc conf
Analysis and Modeling of Stress over Layer Induced Threshold Voltage Shift in HKMG nMOS Transistors.
VLSID
Apoorva Ojha, Narendra Parihar, Nihar R. Mohapatra
2016 — conf
Novel design of a silicon photodetector and its integration in a 4×4 CMOS pixel array.
ISQED
Hari Shanker Gupta, Satyajit Mohapatra, Nihar R. Mohapatra, Dinesh Kumar Sharma
2003 Misc conf
Application of Look-up Table Approach to High-K Gate Dielectric MOS Transistor circuits.
VLSI Design
D. Vinay Kumar, Nihar R. Mohapatra, Mahesh B. Patil, V. Ramgopal Rao
2003 Misc conf
Detailed Analysis of FIBL in MOS Transistors with High-K Gate Dielectrics.
VLSI Design
Nihar R. Mohapatra, Madhav P. Desai, V. Ramgopal Rao
2001 Misc conf
Effect Of Fringing Capacitances In Sub 100 Nm Mosfet's With High-K Gate Dielectrics.
VLSI Design
Nihar R. Mohapatra, Arijit Dutta, Madhav P. Desai, V. Ramgopal Rao
2001 J jnl
Sub-100 nm CMOS circuit performance with high-K gate dielectrics.
Microelectron. Reliab.
Nihar R. Mohapatra, Arijit Dutta, G. Sridhar, Madhav P. Desai, V. Ramgopal Rao