Nicolai Fiege

11 papers B 4Misc 1Journal 5Unranked 1
YearRankTypeTitle / Venue / Authors
2026 J jnl
Discovering Optimal Constant Matrix Multiplication Circuits With Boolean Satisfiability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Nicolai Fiege, Peter Zipf
2025 J jnl
Fantastic Circuits and Where to Find Them - A Holistic ILP Formulation for Model-Based Hardware Design.
ACM Trans. Reconfigurable Technol. Syst.
Nicolai Fiege, Peter Zipf
2025 B conf
Improving Boolean Satisfiability-Based Modulo Scheduling.
FPL
Nicolai Fiege, Peter Zipf
2025 B conf
Multiplexer Optimizations for Virtex FPGAs.
FPL
Nicolai Fiege, Martin Hardieck, Peter Zipf
2024 J jnl
Bit-Level Optimized Constant Multiplication Using Boolean Satisfiability.
IEEE Trans. Circuits Syst. I Regul. Pap.
Nicolai Fiege, Martin Kumm, Peter Zipf
2023 J jnl
BLOOP: Boolean Satisfiability-based Optimized Loop Pipelining.
ACM Trans. Reconfigurable Technol. Syst.
Nicolai Fiege, Peter Zipf
2022 Misc conf
Improving Energy Efficiency in Loop Pipelining by Rational-II Modulo Scheduling.
FCCM
Nicolai Fiege, Patrick Sittel, Peter Zipf
2022 B conf
Optimal Binding and Port Assignment for Loop Pipelining in High-Level Synthesis.
FPL
Nicolai Fiege, Patrick Sittel, Peter Zipf
2022 J jnl
Optimal and Heuristic Approaches to Modulo Scheduling With Rational Initiation Intervals in Hardware Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Patrick Sittel, Nicolai Fiege, John Wickerson, Peter Zipf
2022 B conf
Speeding Up Optimal Modulo Scheduling with Rational Initiation Intervals.
FPL
Nicolai Fiege, Patrick Sittel, Peter Zipf
2019 — conf
Isomorphic Subgraph-based Problem Reduction for Resource Minimal Modulo Scheduling.
ReConFig
Patrick Sittel, Nicolai Fiege, Martin Kumm, Peter Zipf