Nicola Nicolici

137 papers A* 7A 33B 6C 8Misc 1Journal 64Unranked 18

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	An Embedded Architecture for DDR5 DFE Calibration Based on Channel Stimulus Inversion. IEEE Trans. Very Large Scale Integr. Syst. Mitchell Cooke, Nicola Nicolici
2025	J	`jnl`	Interview With Yao-Wen Chang. IEEE Des. Test Nicola Nicolici
2025	J	`jnl`	Karatsuba Matrix Multiplication and Its Efficient Custom Hardware Implementations. IEEE Trans. Computers Trevor E. Pogue, Nicola Nicolici
2025	J	`jnl`	Karatsuba Matrix Multiplication and its Efficient Custom Hardware Implementations. CoRR Trevor E. Pogue, Nicola Nicolici
2025	J	`jnl`	Strassen Multisystolic Array Hardware Architectures. CoRR Trevor E. Pogue, Nicola Nicolici
2025	J	`jnl`	Strassen Multisystolic Array Hardware Architectures. IEEE Trans. Very Large Scale Integr. Syst. Trevor E. Pogue, Nicola Nicolici
2024	J	`jnl`	Fast Inner-Product Algorithms and Architectures for Deep Neural Network Accelerators. IEEE Trans. Computers Trevor E. Pogue, Nicola Nicolici
2024	J	`jnl`	Interview With Janusz Rajski. IEEE Des. Test Nicola Nicolici
2024	J	`jnl`	Interview With Vishwani Agrawal. IEEE Des. Test Nicola Nicolici
2024	J	`jnl`	Thresholding Decision-Directed Descent (T3D): A Tuning Solution for DDR5 DRAM DFEs. IEEE Trans. Very Large Scale Integr. Syst. Mitchell Cooke, Nicola Nicolici
2023	J	`jnl`	Fast Inner-Product Algorithms and Architectures for Deep Neural Network Accelerators. CoRR Trevor E. Pogue, Nicola Nicolici
2023	J	`jnl`	Interview With Janet Olson. IEEE Des. Test Nicola Nicolici
2023	J	`jnl`	Interview With Prof. Sung-Mo (Steve) Kang. IEEE Des. Test Nicola Nicolici
2020	J	`jnl`	Incremental Fault Analysis: Relaxing the Fault Model of Differential Fault Attacks. IEEE Trans. Very Large Scale Integr. Syst. Trevor E. Pogue, Nicola Nicolici
2018	J	`jnl`	Bit-Flip Detection-Driven Selection of Trace Signals. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Amin Vali, Nicola Nicolici
2017	C	`conf`	A generic embedded sequence generator for constrained-random validation with weighted distributions. IOLTS Xiaobing Shi, Nicola Nicolici
2017	A	`conf`	An automated SAT-based method for the design of on-chip bit-flip detectors. ICCAD Pouya Taatizadeh, Nicola Nicolici
2017	J	`jnl`	Emulation Infrastructure for the Evaluation of Hardware Assertions for Post-Silicon Validation. IEEE Trans. Very Large Scale Integr. Syst. Pouya Taatizadeh, Nicola Nicolici
2016	J	`jnl`	Automated Selection of Assertions for Bit-Flip Detection During Post-Silicon Validation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Pouya Taatizadeh, Nicola Nicolici
2016	B	`conf`	Bit-flip detection-driven selection of trace signals. ETS Amin Vali, Nicola Nicolici
2016	J	`jnl`	Generating Cyclic-Random Sequences in a Constrained Space for In-System Validation. IEEE Trans. Computers Xiaobing Shi, Nicola Nicolici
2016	J	`jnl`	Guest Editors' Introduction: Top Papers from the 2015 International Test Conference. IEEE Des. Test Nicola Nicolici, Haralampos-G. D. Stratigopoulos
2016	J	`jnl`	On-Chip Cube-Based Constrained-Random Stimuli Generation for Post-Silicon Validation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xiaobing Shi, Nicola Nicolici
2015	A	`conf`	A methodology for automated design of embedded bit-flips detectors in post-silicon validation. DATE Pouya Taatizadeh, Nicola Nicolici
2015	C	`conf`	Emulation-based selection and assessment of assertion checkers for post-silicon validation. ICCD Pouya Taatizadeh, Nicola Nicolici
2015	A	`conf`	On-Chip Generation of Uniformly Distributed Constrained-Random Stimuli for Post-Silicon Validation. ICCAD Xiaobing Shi, Nicola Nicolici
2015	A	`conf`	SAT Solving using FPGA-based Heterogeneous Computing. ICCAD Jason Thong, Nicola Nicolici
2015	—	`conf`	Satisfiability-Based Analysis of Failing Traces during Post-silicon Debug. NATW Amin Vali, Nicola Nicolici
2014	J	`jnl`	A Multiple-FPGA parallel computing architecture for real-time simulation of soft-object deformation. ACM Trans. Embed. Comput. Syst. Behzad Mahdavikhah, Ramin Mafi, Shahin Sirouspour, Nicola Nicolici
2014	J	`jnl`	A Novel Algorithmic Approach to Aid Post-Silicon Delay Measurement and Clock Tuning. IEEE Trans. Computers Zahra Lak, Nicola Nicolici
2014	—	`conf`	On Supporting Sequential Constraints for On-Chip Generation of Post-silicon Validation Stimuli. ATS Xiaobing Shi, Nicola Nicolici
2014	A	`conf`	On-chip constrained random stimuli generation for post-silicon validation using compact masks. ITC Xiaobing Shi, Nicola Nicolici
2013	A	`conf`	FPGA acceleration of enhanced boolean constraint propagation for SAT solvers. ICCAD Jason Thong, Nicola Nicolici
2013	A*	`conf`	Hardware-efficient on-chip generation of time-extensive constrained-random sequences for in-system validation. DAC Adam B. Kinsman, Ho Fai Ko, Nicola Nicolici
2013	J	`jnl`	NoC-Based FPGA Acceleration for Monte Carlo Simulations with Applications to SPECT Imaging. IEEE Trans. Computers Phillip Kinsman, Nicola Nicolici
2012	—	`conf`	Automated data analysis techniques for a modern silicon debug environment. ASP-DAC Yu-Shen Yang, Andreas G. Veneris, Nicola Nicolici, Masahiro Fujita
2012	J	`jnl`	Automating Data Analysis and Acquisition Setup in a Silicon Debug Environment. IEEE Trans. Very Large Scale Integr. Syst. Yu-Shen Yang, Andreas G. Veneris, Nicola Nicolici
2012	A	`conf`	In-system constrained-random stimuli generation for post-silicon validation. ITC Adam B. Kinsman, Ho Fai Ko, Nicola Nicolici
2012	J	`jnl`	Mapping Trigger Conditions onto Trigger Units during Post-silicon Validation and Debugging. IEEE Trans. Computers Ho Fai Ko, Nicola Nicolici
2012	J	`jnl`	On Using On-Chip Clock Tuning Elements to Address Delay Degradation Due to Circuit Aging. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zahra Lak, Nicola Nicolici
2012	—	`conf`	On-chip stimuli generation for post-silicon validation. HLDVT Nicola Nicolici
2011	—	`conf`	A New Algorithm for Post-Silicon Clock Measurement and Tuning. DFT Zahra Lak, Nicola Nicolici
2011	J	`jnl`	A VLSI Architecture and the FPGA Prototype for MPEG-2 Audio/Video Decoding. IEEE Trans. Very Large Scale Integr. Syst. Adam B. Kinsman, Nicola Nicolici
2011	J	`jnl`	An Optimal and Practical Approach to Single Constant Multiplication. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jason Thong, Nicola Nicolici
2011	J	`jnl`	Automated Range and Precision Bit-Width Allocation for Iterative Computations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Adam B. Kinsman, Nicola Nicolici
2011	J	`jnl`	Computational Vector-Magnitude-Based Range Determination for Scientific Abstract Data Types. IEEE Trans. Computers Adam B. Kinsman, Nicola Nicolici
2011	J	`jnl`	Design-for-Debug Architecture for Distributed Embedded Logic Analysis. IEEE Trans. Very Large Scale Integr. Syst. Ho Fai Ko, Adam B. Kinsman, Nicola Nicolici
2011	A*	`conf`	Dynamic binary translation to a reconfigurable target for on-the-fly acceleration. DAC Phillip Kinsman, Nicola Nicolici
2011	J	`jnl`	Embedded Debug Architecture for Bypassing Blocking Bugs During Post-Silicon Validation. IEEE Trans. Very Large Scale Integr. Syst. Ehab Anis Daoud, Nicola Nicolici
2011	J	`jnl`	Guest Editors' Introduction: Surveying the Landscape of FPGA Accelerator Research. IEEE Des. Test Comput. George A. Constantinides, Nicola Nicolici
2011	A	`conf`	In-system and on-the-fly clock tuning mechanism to combat lifetime performance degradation. ICCAD Zahra Lak, Nicola Nicolici
2011	J	`jnl`	Numerical Data Representations for FPGA-Based Scientific Computing. IEEE Des. Test Comput. George A. Constantinides, Adam B. Kinsman, Nicola Nicolici
2011	J	`jnl`	On Using Lossy Compression for Repeatable Experiments during Silicon Debug. IEEE Trans. Computers Ehab Anis Daoud, Nicola Nicolici
2011	J	`jnl`	Trade-Offs in Test Data Compression and Deterministic X-Masking of Responses. IEEE Trans. Computers Adam B. Kinsman, Nicola Nicolici
2010	J	`jnl`	A Parallel Computing Platform for Real-Time Haptic Interaction with Deformable Bodies. IEEE Trans. Haptics Ramin Mafi, Shahin Sirouspour, Behzad Mahdavikhah, Brian Moody, Kaveh Elizeh, Adam B. Kinsman, Nicola Nicolici
2010	A*	`conf`	A novel optimal single constant multiplication algorithm. DAC Jason Thong, Nicola Nicolici
2010	—	`conf`	Automated silicon debug data analysis techniques for a hardware data acquisition environment. ISQED Yu-Shen Yang, Brian Keng, Nicola Nicolici, Andreas G. Veneris, Sean Safarpour
2010	A	`conf`	Automated trace signals selection using the RTL descriptions. ITC Ho Fai Ko, Nicola Nicolici
2010	J	`jnl`	Bit-Width Allocation for Hardware Accelerators for Scientific Computing Using SAT-Modulo Theory. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Adam B. Kinsman, Nicola Nicolici
2010	C	`conf`	Combined optimal and heuristic approaches for multiple constant multiplication. ICCD Jason Thong, Nicola Nicolici
2010	B	`conf`	Combining scan and trace buffers for enhancing real-time observability in post-silicon debugging. ETS Ho Fai Ko, Nicola Nicolici
2010	A*	`conf`	Embedded memory binding in FPGAs. DAC Kaveh Elizeh, Nicola Nicolici
2010	A	`conf`	Haptic rendering of deformable objects using a multiple FPGA parallel computing architecture. FPGA Behzad Mahdavikhah, Ramin Mafi, Shahin Sirouspour, Nicola Nicolici
2010	—	`conf`	On improving real-time observability for in-system post-silicon debug. LATW Nicola Nicolici
2010	A*	`conf`	Post-silicon validation opportunities, challenges and recent advances. DAC Subhasish Mitra, Sanjit A. Seshia, Nicola Nicolici
2010	A*	`conf`	Robust design methods for hardware accelerators for iterative algorithms in scientific computing. DAC Adam B. Kinsman, Nicola Nicolici
2010	J	`jnl`	Time-Multiplexed Compressed Test of SOC Designs. IEEE Trans. Very Large Scale Integr. Syst. Adam B. Kinsman, Nicola Nicolici
2009	—	`conf`	A 1.5GS/s 4096-point digital spectrum analyzer for space-borne applications. CICC Brian C. Richards, Nicola Nicolici, Henry Chen, Kevin Chao, Robert Abiad, Dan Werthimer, Borivoje Nikolic
2009	J	`jnl`	Algorithms for State Restoration and Trace-Signal Selection for Data Acquisition in Silicon Debug. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ho Fai Ko, Nicola Nicolici
2009	A	`conf`	Automated data analysis solutions to silicon debug. DATE Yu-Shen Yang, Nicola Nicolici, Andreas G. Veneris
2009	C	`conf`	Computational bit-width allocation for operations in vector calculus. ICCD Adam B. Kinsman, Nicola Nicolici
2009	—	`conf`	Design-for-debug for post-silicon validation: Can high-level descriptions help? HLDVT Nicola Nicolici, Ho Fai Ko
2009	A	`conf`	Finite Precision bit-width allocation using SAT-Modulo Theory. DATE Adam B. Kinsman, Nicola Nicolici
2009	J	`jnl`	Real-Time Lossless Compression for Silicon Debug. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ehab Anis Daoud, Nicola Nicolici
2009	B	`conf`	Resource-Efficient Programmable Trigger Units for Post-Silicon Validation. ETS Ho Fai Ko, Nicola Nicolici
2009	J	`jnl`	Time-Efficient Single Constant Multiplication Based on Overlapping Digit Patterns. IEEE Trans. Very Large Scale Integr. Syst. Jason Thong, Nicola Nicolici
2008	—	`conf`	A Novel Automated Scan Chain Division Method for Shift and Capture Power Reduction in Broadside At-Speed Test. ISQED Ho Fai Ko, Nicola Nicolici
2008	J	`jnl`	Automated Scan Chain Division for Reducing Shift and Capture Power During Broadside At-Speed Test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ho Fai Ko, Nicola Nicolici
2008	A	`conf`	Automated Trace Signals Identification and State Restoration for Improving Observability in Post-Silicon Validation. DATE Ho Fai Ko, Nicola Nicolici
2008	A	`conf`	Distributed Embedded Logic Analysis for Post-Silicon Validation of SOCs. ITC Ho Fai Ko, Adam B. Kinsman, Nicola Nicolici
2008	—	`conf`	Embedded Deterministic Test Exploiting Care Bit Clustering and Seed Borrowing. ISQED Adam B. Kinsman, Nicola Nicolici
2008	J	`jnl`	Guest Editorial. J. Electron. Test. Nicola Nicolici, Patrick Girard
2008	A	`conf`	Hardware-based parallel computing for real-time haptic rendering of deformable objects. IROS Ramin Mafi, Shahin Sirouspour, Brian Moody, Behzad Mahdavikhah, Kaveh Elizeh, Adam B. Kinsman, Nicola Nicolici, Mahyar Fotoohi, D. Madill
2008	A	`conf`	On Automated Trigger Event Generation in Post-Silicon Validation. DATE Ho Fai Ko, Nicola Nicolici
2008	B	`conf`	On Bypassing Blocking Bugs during Post-Silicon Validation. ETS Ehab Anis Daoud, Nicola Nicolici
2008	A	`conf`	Power-Aware Testing and Test Strategies for Low Power Devices. DATE Dimitris Gizopoulos, Kaushik Roy, Patrick Girard, Nicola Nicolici, Xiaoqing Wen
2008	J	`jnl`	Scan Division Algorithm for Shift and Capture Power Reduction for At-Speed Test Using Skewed-Load Test Application Strategy. J. Electron. Test. Ho Fai Ko, Nicola Nicolici
2007	J	`jnl`	DATE 07 workshop on diagnostic services in NoCs. IEEE Des. Test Comput. Erik Jan Marinissen, Axel Jantsch, Nicola Nicolici
2007	J	`jnl`	Editorial Silicon Debug and Diagnosis. IET Comput. Digit. Tech. Erik Jan Marinissen, Nicola Nicolici
2007	B	`conf`	Embedded Tutorial on Low Power Test. ETS Nicola Nicolici, Xiaoqing Wen
2007	A	`conf`	Interactive presentation: Low cost debug architecture using lossy compression for silicon debug. DATE Ehab Anis, Nicola Nicolici
2007	A	`conf`	On using lossless compression of debug data in embedded logic analysis. ITC Ehab Anis, Nicola Nicolici
2007	J	`jnl`	Test Wrapper Design and Optimization Under Power Constraints for Embedded Cores With Multiple Clock Domains. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Qiang Xu, Nicola Nicolici, Krishnendu Chakrabarty
2006	J	`jnl`	DFT Infrastructure for Broadside Two-Pattern Test of Core-Based SOCs. IEEE Trans. Computers Qiang Xu, Nicola Nicolici
2006	J	`jnl`	Diagnosis of Logic Circuits Using Compressed Deterministic Data and On-Chip Response Comparison. IEEE Trans. Very Large Scale Integr. Syst. Adam B. Kinsman, Scott Ollivierre, Nicola Nicolici
2006	J	`jnl`	Multifrequency TAM design for hierarchical SOCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Qiang Xu, Nicola Nicolici
2006	C	`conf`	RTL Scan Design for Skewed-Load At-speed Test under Power Constraints. ICCD Ho Fai Ko, Nicola Nicolici
2005	J	`jnl`	Modular SOC testing with reduced wrapper count. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Qiang Xu, Nicola Nicolici
2005	J	`jnl`	Modular and rapid testing of SOCs with unwrapped logic blocks. IEEE Trans. Very Large Scale Integr. Syst. Qiang Xu, Nicola Nicolici
2005	A*	`conf`	Multi-frequency wrapper design and optimization for embedded cores under average power constraints. DAC Qiang Xu, Nicola Nicolici, Krishnendu Chakrabarty
2005	A	`conf`	On concurrent test of wrapped cores and unwrapped logic blocks in SOCs. ITC Qiang Xu, Nicola Nicolici
2005	—	`conf`	Register-transfer level functional scan for hierarchical designs. ASP-DAC Ho Fai Ko, Qiang Xu, Nicola Nicolici
2005	J	`jnl`	Synchronization overhead in SOC compressed test. IEEE Trans. Very Large Scale Integr. Syst. Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici
2005	B	`conf`	Time-multiplexed test data decompression architecture for core-based SOCs with improved utilization of tester channels. ETS Adam B. Kinsman, Nicola Nicolici
2005	J	`jnl`	Wrapper design for multifrequency IP cores. IEEE Trans. Very Large Scale Integr. Syst. Qiang Xu, Nicola Nicolici
2004	C	`conf`	Compressed Embedded Diagnosis of Logic Cores. ICCD Scott Ollivierre, Adam B. Kinsman, Nicola Nicolici
2004	C	`conf`	Functional Illinois Scan Design at RTL. ICCD Ho Fai Ko, Nicola Nicolici
2004	—	`conf`	Functional Scan Chain Design at RTL for Skewed-Load Delay Fault Testing. Asian Test Symposium Ho Fai Ko, Nicola Nicolici
2004	—	`conf`	Multi-Frequency Test Access Mechanism Design for Modular SOC Testing. Asian Test Symposium Qiang Xu, Nicola Nicolici
2004	J	`jnl`	Scan architecture with mutually exclusive scan segment activation for shift- and capture-power reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici
2004	J	`jnl`	Testability Trade-Offs for BIST Data Paths. J. Electron. Test. Nicola Nicolici, Bashir M. Al-Hashimi
2004	A	`conf`	Time/Area Tradeoffs in Testing Hierarchical SOCs With Hard Mega-Cores. ITC Qiang Xu, Nicola Nicolici
2004	A	`conf`	Wrapper Design for Testing IP Cores with Multiple Clock Domains. DATE Qiang Xu, Nicola Nicolici
2003	J	`jnl`	Addressing useless test data in core-based system-on-a-chip test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici
2003	A	`conf`	Delay Fault Testing of Core-Based Systems-on-a-Chi. DATE Qiang Xu, Nicola Nicolici
2003	—	`conf`	Embedded Compact Deterministic Test for IP-Protected Cores. DFT Adam B. Kinsman, Jonathan I. Hewitt, Nicola Nicolici
2003	A	`conf`	Hardware/Software Co-testing of Embedded Memories in Complex SOCs. ICCAD Bai Hong Fang, Qiang Xu, Nicola Nicolici
2003	A	`conf`	On Reducing Wrapper Boundary Register Cells in Modular SOC Testing. ITC Qiang Xu, Nicola Nicolici
2003	J	`jnl`	Power-Conscious Test Synthesis and Scheduling. IEEE Des. Test Comput. Nicola Nicolici, Bashir M. Al-Hashimi
2003	—	`conf`	Power-Constrained Embedded Memory BIST Architecture. DFT Bai Hong Fang, Nicola Nicolici
2003	A	`conf`	Test Data Compression: The System Integrator's Perspective. DATE Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici
2003	J	`jnl`	Variable-length input Huffman coding for system-on-a-chip test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici
2002	A	`conf`	Improving Compression Ratio, Area Overhead, and Test Application Time for System-on-a-Chip Test Data Compression/Decompression. DATE Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici
2002	A	`conf`	Integrated Test Data Decompression and Core Wrapper Design for Low-Cost System-on-a-Chip Testing. ITC Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici
2002	C	`conf`	Low Power Mixed-Mode BIST Based on Mask Pattern Generation Using Dual LFSR Re-Seeding. ICCD Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici
2002	J	`jnl`	Multiple Scan Chains for Power Minimization during Test Application in Sequential Circuits. IEEE Trans. Computers Nicola Nicolici, Bashir M. Al-Hashimi
2002	J	`jnl`	Power profile manipulation: a new approach for reducing test application time under power constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici
2002	—	`conf`	Scan Architecture for Shift and Capture Cycle Power Reduction. DFT Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici
2002	Misc	`conf`	Useless Memory Allocation in System-on-a-Chip Test: Problems and Solutions. VTS Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici
2001	—	`conf`	Power constrained test scheduling using power profile manipulation. ISCAS (5) Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici
2001	A	`conf`	Tackling test trade-offs for BIST RTL data paths: BIST area overhead, test application time and power dissipation. ITC Nicola Nicolici, Bashir M. Al-Hashimi
2001	A	`conf`	Testability trade-offs for BIST RTL data paths: the case for three dimensional design space. DATE Nicola Nicolici, Bashir M. Al-Hashimi
2000	J	`jnl`	BIST hardware synthesis for RTL data paths based on testcompatibility classes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Nicola Nicolici, Bashir M. Al-Hashimi, Andrew D. Brown, Alan Christopher Williams
2000	A	`conf`	Power conscious test synthesis and scheduling for BIST RTL data paths. ITC Nicola Nicolici, Bashir M. Al-Hashimi
2000	A	`conf`	Scan Latch Partitioning into Multiple Scan Chains for Power Minimization in Full Scan Sequential Circuits. DATE Nicola Nicolici, Bashir M. Al-Hashimi
1999	A	`conf`	Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths. DATE Nicola Nicolici, Bashir M. Al-Hashimi
1998	J	`jnl`	Correction to the Proof of Theorem 2 in "Parallel Signature Analysis Design with Bounds on Aliasing". IEEE Trans. Computers Nicola Nicolici, Bashir M. Al-Hashimi