Nicola Da Dalt

27 papers Journal 15Unranked 12

Year	Rank	Type	Title / Venue / Authors
2015	J	`jnl`	Design and implementation of switched coil LC-VCOs in the GHz range using the self-inductance technique. Int. J. Circuit Theory Appl. Federico Cernoia, Davide Ponton, Pierpaolo Palestri, Peter Thurner, Nicola Da Dalt, Giulio Cecco, Luca Selmi
2015	—	`conf`	F6: I/O design at 25Gb/s and beyond: Enabling the future communication infrastructure for big data. ISSCC Ken Chang, Frank O'Mahony, Elad Alon, Hyeon-Min Bae, Nicola Da Dalt, Eric Fluhr
2015	—	`conf`	Low power digitally controlled delay insertion unit and 1% accuracy 100MHz oscillator for precise dead-time insertion in DC-DC converters. ESSCIRC Dmytro Cherniak, Michael Aichner, Roberto Nonis, Nicola Da Dalt
2014	J	`jnl`	An Analysis of Phase Noise in Realigned VCOs. IEEE Trans. Circuits Syst. II Express Briefs Nicola Da Dalt
2014	—	`conf`	F6: Energy-efficient I/O design for next-generation systems. ISSCC Frank O'Mahony, Nicola Da Dalt, Ken Chang, Hisakatsu Yamaguchi, Chulwoo Kim, Elad Alon
2013	—	`conf`	A 2.4psrms-jitter digital PLL with Multi-Output Bang-Bang Phase Detector and phase-interpolator-based fractional-N divider. ISSCC Roberto Nonis, Werner Grollitsch, Thomas Santa, Dmytro Cherniak, Nicola Da Dalt
2013	—	`conf`	An all-digital PLL using random modulation for SSC generation in 65nm CMOS. ISSCC Nicola Da Dalt, Peter Pridnig, Werner Grollitsch
2013	—	`conf`	ES3: High-speed communications on 4 wheels: What's in your next car? ISSCC Nicola Da Dalt, Ajith Amerasekera
2013	J	`jnl`	digPLL-Lite: A Low-Complexity, Low-Jitter Fractional-N Digital PLL Architecture. IEEE J. Solid State Circuits Roberto Nonis, Werner Grollitsch, Thomas Santa, Dmytro Cherniak, Nicola Da Dalt
2011	J	`jnl`	Jitter Noise of Sampled Multitone Signals. IEEE Trans. Circuits Syst. II Express Briefs Martin Clara, Nicola Da Dalt
2010	J	`jnl`	A 0.06 mm IEEE J. Solid State Circuits Stefano Dal Toso, Andrea Bevilacqua, Marc Tiebout, Nicola Da Dalt, Andrea Gerosa, Andrea Neviani
2010	—	`conf`	A 1.4psrms-period-jitter TDC-less fractional-N digital PLL with digitally controlled ring oscillator in 65nm CMOS. ISSCC Werner Grollitsch, Roberto Nonis, Nicola Da Dalt
2010	—	`conf`	A 4.1 to 5.1 GHz 430 μA injection-locked frequency divider by 7 in 65 nm CMOS. ESSCIRC Andrea Bevilacqua, Leonardo Lorenzon, Nicola Da Dalt, Andrea Gerosa, Andrea Neviani
2009	—	`conf`	A 0.059-mm2 10.8-mW local oscillator for GSM systems in 65-nm CMOS. ESSCIRC Stefano Dal Toso, Andrea Bevilacqua, Marc Tiebout, Nicola Da Dalt, Andrea Gerosa, Andrea Neviani
2009	J	`jnl`	A Phase-Domain All-Digital Phase-Locked Loop Architecture Without Reference Clock Retiming. IEEE Trans. Circuits Syst. II Express Briefs Stefan Mendel, Christian Vogel, Nicola Da Dalt
2008	J	`jnl`	Comprehensive Behavioral Modeling of Conventional and Dual-Tuning PLLs. IEEE Trans. Circuits Syst. I Regul. Pap. Luca Bizjak, Nicola Da Dalt, Peter Thurner, Roberto Nonis, Pierpaolo Palestri, Luca Selmi
2008	J	`jnl`	Linearized Analysis of a Digital Bang-Bang PLL and Its Validity Limits Applied to Jitter Transfer and Jitter Generation. IEEE Trans. Circuits Syst. I Regul. Pap. Nicola Da Dalt
2006	—	`conf`	A 10b 10GHz digitlly controlled LC oscillator in 65nm CMOS. ISSCC Nicola Da Dalt, Claus Kropf, Markus Burian, Thomas Hartig, Hermann Eul
2006	J	`jnl`	Markov Chains-Based Derivation of the Phase Detector Gain in Bang-Bang PLLs. IEEE Trans. Circuits Syst. II Express Briefs Nicola Da Dalt
2005	J	`jnl`	A compact triple-band low-jitter digital LC PLL with programmable coil in 130-nm CMOS. IEEE J. Solid State Circuits Nicola Da Dalt, Edwin Thaller, Peter Gregorius, Lajos Gazsi
2005	J	`jnl`	A design-oriented study of the nonlinear dynamics of digital bang-bang PLLs. IEEE Trans. Circuits Syst. I Regul. Pap. Nicola Da Dalt
2005	J	`jnl`	Modeling, design and characterization of a new low-jitter analog dual tuning LC-VCO PLL architecture. IEEE J. Solid State Circuits Roberto Nonis, Nicola Da Dalt, Pierpaolo Palestri, Luca Selmi
2004	—	`conf`	A low jitter triple-band digital LC PLL in 130nm CMOS. ESSCIRC Nicola Da Dalt, Edwin Thaller, Peter Gregorius, Lajos Gazsi
2004	J	`jnl`	Effect of jitter on asynchronous sampling with finite number of samples. IEEE Trans. Circuits Syst. II Express Briefs Nicola Da Dalt
2004	—	`conf`	Modeling, design and characterization of a new low jitter analog dual tuning LC-VCO PLL architecture. ISCAS (4) Roberto Nonis, Nicola Da Dalt, Pierpaolo Palestri, Luca Selmi
2003	J	`jnl`	A subpicosecond jitter PLL for clock generation in 0.12-μm digital CMOS. IEEE J. Solid State Circuits Nicola Da Dalt, Christoph Sandner
2002	J	`jnl`	A fully integrated 2.4-GHz LC-VCO frequency synthesizer with 3-ps jitter in 0.18-μm standard digital CMOS copper technology. IEEE J. Solid State Circuits Nicola Da Dalt, Sven Derksen, Patrizia Greco, Christoph Sandner, Harald Schmid, Klaus Strohmayer