Nick Kanopoulos

37 papers A 2C 2Misc 1Journal 22Unranked 9

Year	Rank	Type	Title / Venue / Authors
2004	—	`conf`	Design Methodology for Rapid Development of SoC ICs Based on an Innovative System Architecture with Emphasis to Timing Closure and Power Consumption Optimization. PATMOS Nick Kanopoulos
2000	—	`conf`	Development of reusable serial FIR filters with reprogrammable coefficients designed for serial dataflow architectures. ICECS Kostas Adaos, George Alexiou, Nick Kanopoulos
1999	—	`ch.`	Testability Concepts and DFT. The VLSI Handbook Nick Kanopoulos
1998	J	`jnl`	A dual rail circuits synthesis environment for the implementation of multiple output boolean functions. Int. J. Circuit Theory Appl. Theodore Karoubalis, George Alexiou, Nick Kanopoulos
1998	C	`conf`	An Extensible, Low Cost Rapid Prototyping Environment Based on a Reconfigurable Set of FPGAs. International Workshop on Rapid System Prototyping Kostas Adaos, George Alexiou, Nick Kanopoulos
1996	—	`conf`	A versatile wireless system for real-time telemetry applications. ICECS Theodoros Antonakopoulos, C. Powers, Nick Kanopoulos
1996	—	`conf`	Automatic synthesis of an 8-bit CPU with 100% on-line error detection capability. ICECS Tassos Markas, E. Edwards, S. Wang, J. Medero, Nick Kanopoulos
1996	—	`conf`	TESPAD: a testability specifications advisor for a structured test methodology. ICECS W. Weber, Michael G. McNamer, Nick Kanopoulos
1995	J	`jnl`	A new efficient dcvs circuit synthesis technique used for an improved implementation of a serial/parallel multiplier. Int. J. Circuit Theory Appl. Theodore Karoubalis, Kostas Adaos, George Alexiou, Nick Kanopoulos
1995	—	`conf`	Flip-flop sharing in standard scan path to enhance delay fault testing of sequential circuits. Asian Test Symposium Jason P. Hurst, Nick Kanopoulos
1995	—	`conf`	Optimal synthesis of differential cascode voltage switch (DCVS) logic circuits using ordered binary decision diagrams (OBDDs). EURO-DAC Theodore Karoubalis, George Alexiou, Nick Kanopoulos
1995	J	`jnl`	Reducing the Time to Market Through Rapid Prototyping - Guest Editors' Introduction. Computer Apostolos Dollas, Nick Kanopoulos
1994	J	`jnl`	Design and DCVS implementation of a self-checking bus-monitor unit for highly reliable fault-tolerant system configurations. IEEE Trans. Very Large Scale Integr. Syst. Tassos Markas, Mark Royals, Nick Kanopoulos
1994	—	`conf`	Design and Implementation of a High-Performance, Modular, Sorting Engine. EDAC-ETC-EUROASIC George Alexiou, Dimitrios Stiliadis, Nick Kanopoulos
1994	J	`jnl`	Multiple boundary scan-paths for minimizing circuit-board test-application time. Microprocess. Microprogramming Theodoros Antonakopoulos, Nick Kanopoulos
1994	J	`jnl`	On the design of a high-performance, expandable, sorting engine. Integr. George Alexiou, Dimitrios Stiliadis, Nick Kanopoulos
1993	J	`jnl`	Efficient board interconnect testing using the split boundary scan register. J. Electron. Test. Nazar S. Haider, Nick Kanopoulos
1993	J	`jnl`	On the design and implementation of a lossless data compression and decompression chip. IEEE J. Solid State Circuits Mark Royals, Tassos Markas, Nick Kanopoulos, John H. Reif, James A. Storer
1992	J	`jnl`	A new serial/parallel two's complement multiplier for vlsi digital signal processing. Int. J. Circuit Theory Appl. George Alexiou, Nick Kanopoulos
1992	J	`jnl`	A user programmable macrocell generator for the IEEE 1149.1 boundary scan standard interface port. Microprocess. Microprogramming Mark Royals, Tassos Markas, Nick Kanopoulos
1992	J	`jnl`	Design and implementation of a totally self-checking 16 × 16 bit array multiplier. Integr. Nick Kanopoulos, Joseph H. Carabetta
1992	J	`jnl`	Design of Self-Checking Circuits Using DCVS Logic: A Case Study. IEEE Trans. Computers Nick Kanopoulos, Dimitris Pantzartzis, Frederick R. Bartram
1992	Misc	`conf`	The split boundary scan register technique for testing board interconnects. VTS Nazar S. Haider, Nick Kanopoulos
1990	J	`jnl`	A bus-monitor unit for fault-tolerant system configurations. Microprocessing and Microprogramming Tassos Markas, Nick Kanopoulos
1990	C	`conf`	Creating the IC palette [ASIC design]. RSP Mark Royals, Tassos Markas, Tianmaw Yang, Nick Kanopoulos
1990	J	`jnl`	On Distributed Fault Simulation. Computer Tassos Markas, Mark Royals, Nick Kanopoulos
1990	J	`jnl`	Testing of differential cascade voltage switch (DCVS) circuits. IEEE J. Solid State Circuits Nick Kanopoulos, Nagesh Vasanthavada
1989	J	`jnl`	A built-in test module for fault isolation. IEEE Des. Test Nagesh Vasanthavada, Nick Kanopoulos
1989	J	`jnl`	On the design of a real-time digital median filter. Microprocessing and Microprogramming J. Dodrill, Nick Kanopoulos
1989	J	`jnl`	The Test Engineer's Assistant: A Support Environment for Hardware Design for Testability. Computer Jill J. Hallenbeck, James R. Cybrynski, Nick Kanopoulos, Tassos Markas, Nagesh Vasanthavada
1988	A	`conf`	CAD Tools for Supporting System Design for Testability. ITC Jill J. Hallenbeck, Nick Kanopoulos, Nagesh Vasanthavada, James W. Watterson
1988	J	`jnl`	Design of a bus-monitor for real-time applications. Microprocess. Microprogramming Nick Kanopoulos, Peter N. Marinos
1988	J	`jnl`	Design of an image edge detection filter using the Sobel operator. IEEE J. Solid State Circuits Nick Kanopoulos, Nagesh Vasanthavada, Robert L. Baker
1987	J	`jnl`	A monolithic scan-line bit producer for real-time image rasterization. Microprocess. Microprogramming Nick Kanopoulos, Nagesh Vasanthavada
1986	—	`conf`	A High-Performance Single-Chip VLSI Signal Processor Architecture. Aegean Workshop on Computing Nick Kanopoulos, Peter N. Marinos
1985	J	`jnl`	A single-chip adaptive delta modulator with optimum performance. Integr. Nick Kanopoulos, Vassilios Makios
1983	A	`conf`	Testing of Bit-Serial Signal Processors. ITC Nick Kanopoulos, G. Thomas Mitchell