Nicholas C. Rumin

21 papers A* 2A 3C 2Journal 11Unranked 3
YearRankTypeTitle / Venue / Authors
2005 — conf
Explicit delay metric for interconnect optimization.
ISCAS (3)
Min Ma, Mourad Oulmane, Nicholas C. Rumin
2001 J jnl
Delay and current estimation in a CMOS inverter with an RC load.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mohamed Hafed, Mourad Oulmane, Nicholas C. Rumin
1999 — conf
An analytical current, delay, and power model for the submicron CMOS inverter.
ICECS
Anas A. Hamoui, Nicholas C. Rumin
1996 — conf
Bounding Switching Activity in CMOS Circuits Using Constraint Resolution.
ED&TC
Jindrich Zejda, Eduard Cerny, S. Shenoy, Nicholas C. Rumin
1994 J jnl
Inverter models of CMOS gates for supply current and delay evaluation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Abdolreza Nabavi-Lishi, Nicholas C. Rumin
1994 C conf
Inverter-based Models for Current Analysis of CMOS Logic Circuits.
ISCAS
Abdolreza Nabavi-Lishi, Nicholas C. Rumin
1993 J jnl
Delay prediction from resistance-capacitance models of general MOS circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Denis Martin, Nicholas C. Rumin
1992 J jnl
Accuracy of magnitude-class calculations in switch-level modeling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Eduard Cerny, John P. Hayes, Nicholas C. Rumin
1992 A conf
Delay and bus current evaluation in CMOS logic circuits.
ICCAD
Abdolreza Nabavi-Lishi, Nicholas C. Rumin
1992 J jnl
Transistor-level estimation of worst-case delays in MOS VLSI circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Michel R. Dagenais, Serge Gaiotti, Nicholas C. Rumin
1991 J jnl
A fault-tolerant array processor designed for testability and self-reconfiguration.
IEEE J. Solid State Circuits
Ajai Jain, Babu Mandava, Janusz Rajski, Nicholas C. Rumin
1991 J jnl
A recursive technique for computing delays in series-parallel MOS transistor circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jean Paul Caisso, Eduard Cerny, Nicholas C. Rumin
1989 C conf
Magnitude classes in switch-level modeling.
ICCD
Eduard Cerny, John P. Hayes, Nicholas C. Rumin
1989 J jnl
On the calculation of optimal clocking parameters in synchronous circuits with level-sensitive latches.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Michel R. Dagenais, Nicholas C. Rumin
1989 A* conf
Worst-case Delay Estimation of Transistor Groups.
DAC
Serge Gaiotti, Michel R. Dagenais, Nicholas C. Rumin
1988 A conf
Delay computation in switch-level models of non-treelike MOS circuits.
ICCAD
Denis Martin, Nicholas C. Rumin
1986 J jnl
A Theory for the Design of Soft-Error-Tolerant VLSI Circuits.
IEEE J. Sel. Areas Commun.
Yvon Savaria, Jeremiah F. Hayes, Nicholas C. Rumin, Vinod K. Agarwal
1986 J jnl
McBOOLE: A New Procedure for Exact Logic Minimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Michel R. Dagenais, Vinod K. Agarwal, Nicholas C. Rumin
1986 J jnl
Soft-error filtering: A solution to the reliability problem of future VLSI digital circuits.
Proc. IEEE
Yvon Savaria, Nicholas C. Rumin, Jeremiah F. Hayes, Vinold K. Agarwal
1985 A* conf
The McBOOLE logic minimizer.
DAC
Michel R. Dagenais, Vinod K. Agarwal, Nicholas C. Rumin
1984 A conf
A Design for Machines with Built-In Tolerance to Soft Errors.
ITC
Yvon Savaria, Vinod K. Agarwal, Nicholas C. Rumin, Jeremiah F. Hayes