Nestoras Tzartzanis

22 papers A* 1A 3C 1Journal 10Unranked 7
YearRankTypeTitle / Venue / Authors
2010 J jnl
A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS.
IEEE J. Solid State Circuits
Nikola Nedovic, Anders Kristensson, Samir Parikh, Subodh M. Reddy, Scott McLeod, Nestoras Tzartzanis, Kouichi Kanda, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Takayuki Shibasaki, Yasumoto Tomita, Takayuki Hamada, Mariko Sugawara, Tadashi Ikeuchi, Naoki Kuwata, Hirotaka Tamura, Junji Ogawa, William W. Walker
2009 J jnl
A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS.
IEEE J. Solid State Circuits
Kouichi Kanda, Hirotaka Tamura, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Takayuki Shibasaki, Nestoras Tzartzanis, Anders Kristensson, Samir Parikh, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Mariko Sugawara, Naoki Kuwata, Tadashi Ikeuchi, Junji Ogawa, William W. Walker
2009 — conf
A single-40Gb/s dual-20Gb/s serializer IC with SFI-5.2 interface in 65nm CMOS.
ISSCC
Kouichi Kanda, Hirotaka Tamura, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Takayuki Shibasaki, Nestoras Tzartzanis, Anders Kristensson, Samir Parikh, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Mariko Sugawara, Naoki Kuwata, Tadashi Ikeuchi, Junji Ogawa, William W. Walker
2007 J jnl
A 40-44 Gb/s 3 × Oversampling CMOS CDR/1: 16 DEMUX.
IEEE J. Solid State Circuits
Nikola Nedovic, Nestoras Tzartzanis, Hirotaka Tamura, Francis M. Rotella, Magnus Wiklund, Yuma Mizutani, Yusuke Okaniwa, Tadahiro Kuroda, Junji Ogawa, William W. Walker
2007 — conf
A 40-to-44Gb/s 3�? Oversampling CMOS CDR/1: 16 DEMUX.
ISSCC
Nikola Nedovic, Nestoras Tzartzanis, Hirotaka Tamura, Francis M. Rotella, Magnus Wiklund, Yuma Mizutani, Yusuke Okaniwa, Tadahiro Kuroda, Junji Ogawa, William W. Walker
2007 J jnl
A Leakage Current Replica Keeper for Dynamic Circuits.
IEEE J. Solid State Circuits
Yolin Lih, Nestoras Tzartzanis, William W. Walker
2006 — conf
A Reversible Poly-Phase Distributed VCO.
ISSCC
Nestoras Tzartzanis, William W. Walker
2006 — conf
A leakage current replica keeper for dynamic circuits.
ISSCC
Yolin Lih, Nestoras Tzartzanis, William W. Walker
2005 J jnl
A 40-Gb/s CMOS clocked comparator with bandwidth modulation technique.
IEEE J. Solid State Circuits
Yusuke Okaniwa, Hirotaka Tamura, Masaya Kibune, Daisuke Yamazaki, Tsz-Shing Cheung, Junji Ogawa, Nestoras Tzartzanis, William W. Walker, Tadahiro Kuroda
2005 J jnl
A Case Study: Power and Performance Improvement of a Chip Multiprocessor for Transaction Processing.
IEEE Trans. Very Large Scale Integr. Syst.
Hisashige Ando, Nestoras Tzartzanis, William W. Walker
2005 J jnl
Differential current-mode sensing for efficient on-chip global signaling.
IEEE J. Solid State Circuits
Nestoras Tzartzanis, William W. Walker
2003 C conf
A Transparent Voltage Conversion Method and Its Application to a Dual-Supply-Voltage Register File.
ICCD
Nestoras Tzartzanis, William W. Walker
2000 J jnl
The design and implementation of a low-power clock-powered microprocessor.
IEEE J. Solid State Circuits
William C. Athas, Nestoras Tzartzanis, Weihua Mao, Lena Peterson, Rajat Lal, Kisup Chong, Joong-Seok Moon, Lars J. Svensson, Michael Bolotski
1999 — conf
Clock-Powered CMOS: A Hybrid Adiabatic Logic Style for Energy-Efficient Computing.
ARVLSI
Nestoras Tzartzanis, William C. Athas
1999 A conf
Retractile clock-powered logic.
ISLPED
Nestoras Tzartzanis, William C. Athas
1997 J jnl
A low-power microprocessor based on resonant energy.
IEEE J. Solid State Circuits
William C. Athas, Nestoras Tzartzanis, Lars J. Svensson, Lena Peterson
1997 A conf
AC-1: a clock-powered microprocessor.
ISLPED
William C. Athas, Nestoras Tzartzanis, Lars J. Svensson, Lena Peterson, Huimin Li, Xing Yu Jiang, Peiqing Wang, Weichuan Liu
1996 A conf
Energy recovery for the design of high-speed, low-power static RAMs.
ISLPED
Nestoras Tzartzanis, William C. Athas
1995 — conf
Design and analysis of a low-power energy-recovery adder.
Great Lakes Symposium on VLSI
Nestoras Tzartzanis, William C. Athas
1995 — conf
Energy recovery for low-power CMOS.
ARVLSI
William C. Athas, Nestoras Tzartzanis
1994 J jnl
Low-power digital systems based on adiabatic-switching principles.
IEEE Trans. Very Large Scale Integr. Syst.
William C. Athas, Lars J. Svensson, Jefferey G. Koller, Nestoras Tzartzanis, E. Ying-Chin Chou
1991 A* conf
Reducing the Branch Penalty by Rearranging Instructions in Double-Width Memory.
ASPLOS
Manolis Katevenis, Nestoras Tzartzanis