Nereo Markulic

30 papers C 1Journal 11Unranked 18

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	11.5 A Compact 7b 175GS/s Linearized Time-Interleaved Slope ADC with Switched Input Buffers. ISSCC Ewout Martens, Angelo Parisi, Anirudh Kankuppe, Adam Cooman, Hanyue Li, Steven Van Winckel, Pratap Tumkur Renukaswamy, Lucas Moura Santana, Jorge Lagos, Nereo Markulic, Jan Craninckx
2024	—	`conf`	22.5 A 42GS/s 7b 16nm Massively Time-Interleaved Slope-ADC. ISSCC Ewout Martens, Adam Cooman, Pratap Tumkur Renukaswamy, Shun Nagata, SeHoon Park, Jorge-Luis Lagos, Nereo Markulic, Jan Craninckx
2024	—	`conf`	A 10GS/s Hierarchical Time-Interleaved ADC for RF-Sampling Applications. VLSI Technology and Circuits Nereo Markulic, Johan Nguyen, Jorge Luis Lagos-Benites, Ewout Martens, Jan Craninckx
2024	J	`jnl`	A 16-GHz Background-Calibrated Duty-Cycled FMCW Charge-Pump PLL. IEEE J. Solid State Circuits Pratap Tumkur Renukaswamy, Kristof Vaesen, Nereo Markulic, Jan Craninckx
2024	—	`conf`	A Single-Channel, 1-GS/s, 10.91-ENOB, 81-dB SFDR, 9.2-fJ/conv.-step, Ringamp-Based Pipelined ADC with Background Calibration in 16nm CMOS. VLSI Technology and Circuits Jorge Lagos, Pratap Tumkur Renukaswamy, Nereo Markulic, Ewout Martens, Jan Craninckx
2023	J	`jnl`	A 12-bit 1GS/s ADC With Background Distortion and Split-ADC-Like Gain Calibration. IEEE Trans. Circuits Syst. I Regul. Pap. Lai Wei, Zihao Zheng, Nereo Markulic, Jorge Lagos, Ewout Martens, Rui Paulo Martins, Yan Zhu, Jan Craninckx, Chi-Hang Chan
2023	—	`conf`	A 16GHz, $41\text{kHz}_{\text{rms}}$ Frequency Error, Background-Calibrated, Duty-Cycled FMCW Charge-Pump PLL. ISSCC Pratap Tumkur Renukaswamy, Kristof Vaesen, Nereo Markulic, Veerle Derudder, Dae-Woong Park, Piet Wambacq, Jan Craninckx
2023	—	`conf`	Calibration Techniques for Optimizing Performance of High-Speed ADCs. CICC Ewout Martens, Nereo Markulic, Jorge Luis Lagos-Benites, Jan Craninckx
2022	J	`jnl`	A 10.1-ENOB, 6.2-fJ/conv.-step, 500-MS/s, Ringamp-Based Pipelined-SAR ADC With Background Calibration and Dynamic Reference Regulation in 16-nm CMOS. IEEE J. Solid State Circuits Jorge Lagos, Nereo Markulic, Benjamin P. Hershberg, Davide Dermit, Mithlesh Shrivas, Ewout Martens, Jan Craninckx
2021	J	`jnl`	A 1-MS/s to 1-GS/s Ringamp-Based Pipelined ADC With Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16 nm. IEEE J. Solid State Circuits Benjamin P. Hershberg, Nereo Markulic, Jorge Lagos, Ewout Martens, Davide Dermit, Jan Craninckx
2021	—	`conf`	A 10.0 ENOB, 6.2 fJ/conv.-step, 500 MS/s Ringamp-Based Pipelined-SAR ADC with Background Calibration and Dynamic Reference Regulation in 16nm CMOS. VLSI Circuits Jorge Lagos, Nereo Markulic, Benjamin P. Hershberg, Davide Dermit, Mithlesh Shrivas, Ewout Martens, Jan Craninckx
2021	J	`jnl`	A 4-GS/s 10-ENOB 75-mW Ringamp ADC in 16-nm CMOS With Background Monitoring of Distortion. IEEE J. Solid State Circuits Benjamin P. Hershberg, Davide Dermit, Barend van Liempd, Ewout Martens, Nereo Markulic, Jorge Lagos, Jan Craninckx
2021	—	`conf`	An Auxiliary-Channel-Sharing Background Distortion and Gain Calibration Achieving >8dB SFDR Improvement over 4 VLSI Circuits Lai Wei, Zihao Zheng, Nereo Markulic, Jorge Lagos, Ewout Martens, Yan Zhu, Chi-Hang Chan, Jan Craninckx, Rui Paulo Martins
2021	J	`jnl`	Asynchronous Event-Driven Clocking and Control in Pipelined ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. Benjamin P. Hershberg, Barend van Liempd, Nereo Markulic, Jorge Lagos, Ewout Martens, Davide Dermit, Jan Craninckx
2021	C	`conf`	Fractional-N Sub-Sampling PLL Using a Calibrated Delay Line for Phase Noise Cancellation. ISCAS Pratap Tumkur Renukaswamy, Nereo Markulic, Piet Wambacq, Jan Craninckx
2020	—	`conf`	17.7 A 12mW 10GHz FMCW PLL Based on an Integrating DAC with 90kHz rms Frequency Error for 23MHz/µs Slope and 1.2GHz Chirp Bandwidth. ISSCC Pratap Tumkur Renukaswamy, Nereo Markulic, SeHoon Park, Anirudh Kankuppe, Qixian Shi, Piet Wambacq, Jan Craninckx
2020	J	`jnl`	A 12-mW 10-GHz FMCW PLL Based on an Integrating DAC With 28-kHz RMS-Frequency-Error for 23-MHz/μs Slope and 1.2-GHz Chirp-Bandwidth. IEEE J. Solid State Circuits Pratap Tumkur Renukaswamy, Nereo Markulic, Piet Wambacq, Jan Craninckx
2020	—	`conf`	A 1MS/s to 1GS/s Ringamp-Based Pipelined ADC with Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16nm. VLSI Circuits Benjamin P. Hershberg, Nereo Markulic, Jorge Lagos, Ewout Martens, Davide Dermit, Jan Craninckx
2019	—	`conf`	A 3.2GS/s 10 ENOB 61mW Ringamp ADC in 16nm with Background Monitoring of Distortion. ISSCC Benjamin P. Hershberg, Davide Dermit, Barend van Liempd, Ewout Martens, Nereo Markulic, Jorge Lagos, Jan Craninckx
2019	J	`jnl`	A 5.5-GHz Background-Calibrated Subsampling Polar Transmitter With -41.3-dB EVM at 1024 QAM in 28-nm CMOS. IEEE J. Solid State Circuits Nereo Markulic, Pratap Tumkur Renukaswamy, Ewout Martens, Barend van Liempd, Piet Wambacq, Jan Craninckx
2019	—	`conf`	A 6-to-600MS/s Fully Dynamic Ringamp Pipelined ADC with Asynchronous Event-Driven Clocking in 16nm. ISSCC Benjamin P. Hershberg, Barend van Liempd, Nereo Markulic, Jorge Lagos, Ewout Martens, Davide Dermit, Jan Craninckx
2019	J	`jnl`	A Self-Calibrated 16-GHz Subsampling-PLL-Based Fast-Chirp FMCW Modulator With 1.5-GHz Bandwidth. IEEE J. Solid State Circuits Qixian Shi, Keigo Bunsen, Nereo Markulic, Jan Craninckx
2019	—	`conf`	A Self-Calibrated 16GHz Subsampling-PLL-Based 30s Fast Chirp FMCW Modulator with 1.5GHz Bandwidth and 100kHz rms Error. ISSCC Qixian Shi, Keigo Bunsen, Nereo Markulic, Jan Craninckx
2018	—	`conf`	A 5.5 GHz Background-Calibrated Subsampling Polar Transmitter with -41.3 DB EVM at 1024 OAM in 28NM CMOS. VLSI Circuits Nereo Markulic, Pratap Renukaswarny, Ewout Martens, Barend van Liempd, Piet Wambacq, Jan Craninckx
2017	—	`conf`	24.7 A 673µW 1.8-to-2.5GHz dividerless fractional-N digital PLL with an inherent frequency-capture capability and a phase-dithering spur mitigation for IoT applications. ISSCC Yuming He, Yao-Hong Liu, Takashi Kuramochi, Johan H. C. van den Heuvel, Benjamin Busze, Nereo Markulic, Christian Bachmann, Kathleen Philips
2016	—	`conf`	9.7 A self-calibrated 10Mb/s phase modulator with -37.4dB EVM based on a 10.1-to-12.4GHz, -246.6dB-FOM, fractional-N subsampling PLL. ISSCC Nereo Markulic, Kuba Raczkowski, Ewout Martens, Pedro Emiliano Paro Filho, Benjamin P. Hershberg, Piet Wambacq, Jan Craninckx
2016	J	`jnl`	A DTC-Based Subsampling PLL Capable of Self-Calibrated Fractional Synthesis and Two-Point Modulation. IEEE J. Solid State Circuits Nereo Markulic, Kuba Raczkowski, Ewout Martens, Pedro Emiliano Paro Filho, Benjamin P. Hershberg, Piet Wambacq, Jan Craninckx
2016	—	`conf`	A Fractional-n subsampling PLL based on a digital-to-time converter. MIPRO Nereo Markulic, Kuba Raczkowski, Piet Wambacq, Jan Craninckx
2015	J	`jnl`	A 9.2-12.7 GHz Wideband Fractional-N Subsampling PLL in 28 nm CMOS With 280 fs RMS Jitter. IEEE J. Solid State Circuits Kuba Raczkowski, Nereo Markulic, Benjamin P. Hershberg, Jan Craninckx
2014	—	`conf`	A 10-bit, 550-fs step Digital-to-Time Converter in 28nm CMOS. ESSCIRC Nereo Markulic, Kuba Raczkowski, Piet Wambacq, Jan Craninckx