Nelson H. C. Yung

58 papers A 2B 7C 3Misc 5Journal 31Unranked 10
YearRankTypeTitle / Venue / Authors
2018 J jnl
Inf. Sci.
Li-Li Wang, Henry Y. T. Ngan, Nelson H. C. Yung
2018 conf
IRIACV
Philip Lam, Lili Wang, Henry Y. T. Ngan, Nelson H. C. Yung, Michael K. Ng
2017 J jnl
IEEE Trans. Geosci. Remote. Sens.
Xing Sun, Nelson H. C. Yung, Edmund Y. Lam, Hayden Kwok-Hay So
2017 J jnl
Mach. Vis. Appl.
Chongguo Li, Nelson H. C. Yung, Xing Sun, Edmund Y. Lam
2017 conf
IRIACV
Philip Lam, Lili Wang, Henry Y. T. Ngan, Nelson H. C. Yung, Anthony G. O. Yeh
2016 Misc conf
DICTA
Li-Li Wang, Henry Y. T. Ngan, Wei Liu, Nelson H. C. Yung
2016 J jnl
J. Signal Process. Syst.
Chongguo Li, Nelson H. C. Yung
2016 J jnl
CoRR
Xing Sun, Nelson H. C. Yung, Edmund Y. Lam, Hayden Kwok-Hay So
2016 J jnl
IEEE Trans. Intell. Transp. Syst.
Xing Sun, Nelson H. C. Yung, Edmund Y. Lam
2016 conf
Image Processing: Machine Vision Applications
Xing Sun, Nelson H. C. Yung, Edmund Y. Lam, Hayden K. H. So
2015 conf
Image Processing: Machine Vision Applications
Henry Y. T. Ngan, Nelson H. C. Yung, Anthony G. O. Yeh
2015 J jnl
CoRR
Li-Li Wang, Henry Y. T. Ngan, Nelson H. C. Yung
2015 J jnl
Mach. Vis. Appl.
Chongguo Li, Nelson H. C. Yung
2015 Misc conf
MVA
Chongguo Li, Nelson H. C. Yung, Edmund Y. Lam
2015 J jnl
J. Vis. Commun. Image Represent.
Li-Li Wang, Nelson H. C. Yung
2015 J jnl
Mach. Vis. Appl.
Li-Li Wang, Nelson H. C. Yung
2015 J jnl
CoRR
Philip Lam, Li-Li Wang, Henry Y. T. Ngan, Nelson H. C. Yung, Anthony Gar-On Yeh
2014 conf
VISAPP (2)
Chongguo Li, Nelson H. C. Yung
2014 J jnl
Mach. Vis. Appl.
Shan-shan Zhu, Nelson H. C. Yung
2014 B conf
ICPR
Xing Sun, Nelson H. C. Yung
2014 J jnl
J. Vis. Commun. Image Represent.
Shan-shan Zhu, Nelson H. C. Yung
2012 J jnl
Pattern Recognit.
Jianzhao Qin, Nelson H. C. Yung
2012 conf
CASE
Henry Y. T. Ngan, Nelson H. C. Yung, Anthony Gar-On Yeh
2012 J jnl
IEEE Trans. Intell. Transp. Syst.
Lu Wang, Nelson H. C. Yung
2011 J jnl
IEEE Trans. Intell. Transp. Syst.
Daniel Chi Kit Ngai, Nelson H. C. Yung
2011 J jnl
Pattern Recognit.
Zhuo Chen, Lu Wang, Nelson H. C. Yung
2011 J jnl
Image Vis. Comput.
Henry Y. T. Ngan, Grantham K. H. Pang, Nelson H. C. Yung
2011 A conf
WACV
Lu Wang, Nelson H. C. Yung
2011 Misc conf
MVA
Zhuo Chen, Nelson H. C. Yung
2011 J jnl
IEEE Trans. Intell. Transp. Syst.
C. Y. Liu, Nelson H. C. Yung
2011 A conf
ICME
Shan-shan Zhu, Nelson H. C. Yung
2010 B conf
ICIP
Jianzhao Qin, Nelson H. C. Yung
2010 B conf
ICPR
Lu Wang, Nelson H. C. Yung
2010 J jnl
Pattern Recognit.
Henry Y. T. Ngan, Grantham K. H. Pang, Nelson H. C. Yung
2010 J jnl
IEEE Trans. Intell. Transp. Syst.
Lu Wang, Nelson H. C. Yung
2010 J jnl
Pattern Recognit.
Jianzhao Qin, Nelson H. C. Yung
2009 B conf
ICIP
Lu Wang, Nelson H. C. Yung
2009 conf
ISVC (1)
Jianzhao Qin, Nelson H. C. Yung
2008 B conf
ICPR
Zhigang Tan, Nelson H. C. Yung
2008 J jnl
Pattern Recognit.
Henry Y. T. Ngan, Grantham K. H. Pang, Nelson H. C. Yung
2007 J jnl
IEEE Trans. Intell. Transp. Syst.
Clement Chun Cheong Pang, William Wai Leung Lam, Nelson H. C. Yung
2007 conf
ITSC
Daniel C. K. Ngai, Nelson H. C. Yung
2007 conf
MLDM
Daniel C. K. Ngai, Nelson H. C. Yung
2007 conf
ICIP (2)
Henry Y. T. Ngan, Grantham K. H. Pang, Nelson H. C. Yung
2007 J jnl
IEEE Trans. Intell. Transp. Syst.
William Wai Leung Lam, Clement Chun Cheong Pang, Nelson H. C. Yung
2006 C conf
PSIVT
Zhigang Tan, Xiao-Chen He, Nelson H. C. Yung
2005 B conf
SMC
Daniel Chi Kit Ngai, Nelson H. C. Yung
2004 J jnl
IEEE Trans. Intell. Transp. Syst.
Clement Chun Cheong Pang, William Wai Leung Lam, Nelson H. C. Yung
2004 J jnl
Pattern Recognit.
Xuezhi Yang, Grantham Pang, Nelson H. C. Yung
2004 B conf
ICIP
William Wai Leung Lam, Clement Chun Cheong Pang, Nelson H. C. Yung
2002 C conf
ICARCV
Hing Y. Chung, Nelson H. C. Yung, Paul Y. S. Cheung
2001 C conf
VCIP
Kwong-Keung Leung, Nelson H. C. Yung, Paul Y. S. Cheung
2001 J jnl
IEEE Trans. Veh. Technol.
Nelson H. C. Yung, Andrew H. S. Lai
2001 Misc conf
ICASSP
Yang Xue Zhi, Grantham K. H. Pang, Nelson H. C. Yung
2001 J jnl
IEEE Trans. Circuits Syst. Video Technol.
Kwong-Keung Leung, Nelson H. C. Yung
2000 J jnl
IEEE Trans. Circuits Syst. Video Technol.
Kwong-Keung Leung, Nelson H. C. Yung, Paul Y. S. Cheung
2000 J jnl
IEEE Trans. Intell. Transp. Syst.
Andrew H. S. Lai, Nelson H. C. Yung
1998 Misc conf
MVA
Andrew H. S. Lai, Nelson H. C. Yung
redb/extractors/decompiler/bninja/arch/x86.py
← Index redb/extractors/decompiler/bninja/arch/x86.py python
from binaryninja.enums import (
    InstructionTextTokenType,
)

# Support both package and standalone imports
try:
    from .architecture import Architecture
except ImportError:
    # Fallback to absolute imports (for multiprocessing spawned processes)
    from redb.extractors.decompiler.bninja.arch.architecture import Architecture


class Arch_x86(Architecture):
    """The concrete class for architecture-dependent details for x86_64"""

    def __init__(self):
        # general purpose registers for 64bits
        self.gpr_64 = [
            "RAX",
            "RBX",
            "RCX",
            "RDX",
            "RSI",
            "RDIR9",
            "R10",
            "R11",
            "R12",
            "R13",
            "R14",
            "R15",
        ]

        self.gpr_32 = [
            "EAX",
            "EBX",
            "ECX",
            "EDX",
            "ESI",
            "EDI",
            "R8D",
            "R9D",
            "R10D",
            "R11D",
            "R12D",
            "R13D",
            "R14D",
            "R15D",
        ]

        self.gpr_16 = [
            "AX",
            "BX",
            "CX",
            "DX",
            "SI",
            "DI",
            "R8W",
            "R9W",
            "R10W",
            "R11W",
            "R12W",
            "R13W",
            "R14W",
            "R15W",
        ]

        self.gpr_8 = [
            "AL",
            "BL",
            "CL",
            "DL",
            "SIL",
            "DIL",
            "R8B",
            "R9B",
            "R10B",
            "R11B",
            "R12B",
            "R13B",
            "R14B",
            "R15B",
        ]

        self.fpu_x87 = ["ST0", "ST1", "ST2", "ST3", "ST4", "ST5", "ST6", "ST7"]

        self.sse_xmm = [
            "XMM0",
            "XMM1",
            "XMM2",
            "XMM3",
            "XMM4",
            "XMM5",
            "XMM6",
            "XMM7",
            "XMM8",
            "XMM9",
            "XMM10",
            "XMM11",
            "XMM12",
            "XMM13",
            "XMM14",
            "XMM15",
        ]

        self.avx_ymm = [
            "YMM0",
            "YMM1",
            "YMM2",
            "YMM3",
            "YMM4",
            "YMM5",
            "YMM6",
            "YMM7",
            "YMM8",
            "YMM9",
            "YMM10",
            "YMM11",
            "YMM12",
            "YMM13",
            "YMM14",
            "YMM15",
        ]
        self.flags = ["FLAGS", "EFLAGS", "RFLAGS"]
        self.stack_registers = ["RBP", "RSP", "SP", "BP"]
        self.size = 8
        self.global_registers = (
            self.gpr_64
            + self.gpr_32
            + self.gpr_16
            + self.gpr_8
            + self.fpu_x87
            + self.sse_xmm
            + self.avx_ymm
        )
        self.opcode_categories = self._initialize_opcode_categories()

        ## instructions
        self.instructions = []

    def is_register(self, register):
        register = register.upper()
        return register in self.global_registers

    def is_general_purpose_register(self, register):
        register = register.upper()
        return (
            register in self.gpr_64
            or register in self.gpr_32
            or register in self.gpr_16
            or register in self.gpr_8
        )

    def is_stack_register(self, register):
        register = register.upper()
        return register in self.stack_registers

    def is_xmm_register(self, register):
        register = register.upper()
        return register in self.sse_xmm

    def is_control_flow(self, instr_tokens):
        return False

    def is_control_flow_instruction(self, instr_tokens):
        """Check if an instruction is a control flow instruction (jump, call, return, loop)."""
        try:
            # Extract the mnemonic from the instruction tokens
            mnemonic = None
            for token in instr_tokens:
                if token.type == InstructionTextTokenType.InstructionToken:
                    mnemonic = token.text.upper()
                    break

            if not mnemonic:
                return False

            # Check if it's a jump, call, return, or loop instruction
            return (
                mnemonic.startswith("J")  # All jumps (JMP, JE, JNE, etc.)
                or mnemonic == "CALL"  # Function calls
                or mnemonic == "RET"  # Return
                or mnemonic == "RETN"  # Another form of return
                or mnemonic.startswith("LOOP")
            )  # Loop instructions

        except Exception as e:
            print(e)
            # If we can't determine, assume it's not a control flow instruction
            return False

    def is_control_flow_instruction_by_mnemonic(self, mnemonic):
        """Check if an instruction is a control flow instruction based on its mnemonic."""
        if not mnemonic:
            return False

        mnemonic = mnemonic.upper()
        return (
            mnemonic.startswith("J")  # All jumps (JMP, JE, JNE, etc.)
            or mnemonic == "CALL"  # Function calls
            or mnemonic == "RET"  # Return
            or mnemonic == "RETN"  # Another form of return
            or mnemonic.startswith("LOOP")
        )

    def _initialize_opcode_categories(self):
        """Initialize mapping of opcodes to categories similar to Ghidra's implementation."""
        opcode_categories = {}
        opcode_index = {}  # Add this to mimic Ghidra's opcodeIndex

        # Define common opcodes array similar to Ghidra's COMMON_OPCODES
        COMMON_OPCODES = [
            # Core instructions (tracked individually)
            "MOV",
            "PUSH",
            "POP",
            "LEA",
            "CALL",
            "RET",  # Data movement and control
            "ADD",
            "SUB",
            "MUL",
            "DIV",  # Basic arithmetic
            "AND",
            "OR",
            "XOR",
            "NOT",  # Logical operations
            "JMP",
            "JE",
            "JNE",  # Basic jumps
            "TEST",
            "CMP",  # Comparisons
            # Grouped categories (aggregated tracking)
            "SIMD_MOVE",  # MOVAPS, MOVDQA, MOVDQU, etc.
            "COND_JUMP_EXT",  # Other conditional jumps (JG, JL, JGE, etc.)
            "STRING_OP",  # MOVS, STOS, LODS, SCAS, CMPS
            "STACK_ADV",  # ENTER, LEAVE, PUSHA, POPA
            "ARITHMETIC_ADV",  # IMUL, IDIV, ADC, SBB
            "BIT_OP",  # SHL, SHR, SAR, ROL, ROR, etc.
            "FPU_OP",  # FLD, FST, FADD, etc.
            "SYSTEM_OP",  # SYSCALL, INT, SYSENTER
            "CRYPTO_OP",  # AES*, SHA* instructions
            "MISC_OP",  # Rare but interesting (CPUID, RDTSC, etc.)
        ]

        # Create index map like Ghidra
        for i, opcode in enumerate(COMMON_OPCODES):
            opcode_index[opcode] = i

        # Now categorize opcodes using if/elif/else structure like in Ghidra
        for opcode in COMMON_OPCODES:
            # String Operations (checking these first to avoid MOV confusion)
            if opcode.startswith("MOVS") or opcode in [
                "STOS",
                "LODS",
                "SCAS",
                "CMPS",
                "REP",
                "REPE",
                "REPNE",
            ]:
                opcode_categories[opcode] = "STRING_MANIPULATION"

            # Data Movement (after string ops to avoid MOVS confusion)
            elif opcode.startswith("MOV") or opcode in ["LEA", "XCHG"]:
                opcode_categories[opcode] = "DATA_MOVEMENT"

            # Stack Operations
            elif opcode in ["PUSH", "POP", "ENTER", "LEAVE", "PUSHA", "POPA"]:
                opcode_categories[opcode] = "STACK_MANAGEMENT"

            # Control Flow (non-conditional)
            elif opcode in ["JMP", "CALL", "RET"]:
                opcode_categories[opcode] = "CONTROL_FLOW"

            # Conditional Jumps and Loops
            elif opcode.startswith("J") or opcode.startswith("LOOP"):
                opcode_categories[opcode] = "CONDITIONAL_JUMP"

            # Arithmetic
            elif opcode in [
                "ADD",
                "SUB",
                "MUL",
                "DIV",
                "IMUL",
                "IDIV",
                "ADC",
                "SBB",
                "INC",
                "DEC",
                "NEG",
            ]:
                opcode_categories[opcode] = "ARITHMETIC"

            # Logical
            elif opcode in ["AND", "OR", "XOR", "NOT", "TEST", "CMP"]:
                opcode_categories[opcode] = "LOGICAL"

            # Shifts & Rotates
            elif opcode in ["SHL", "SHR", "SAR", "SAL", "ROL", "ROR", "RCL", "RCR"]:
                opcode_categories[opcode] = "SHIFT_ROTATE"

            # System & Interrupts
            elif opcode in [
                "SYSCALL",
                "INT",
                "SYSENTER",
                "SYSEXIT",
                "SGDT",
                "SIDT",
                "SLDT",
                "WRMSR",
                "RDMSR",
            ]:
                opcode_categories[opcode] = "SYSTEM_CALLS"

            # Floating Point
            elif opcode.startswith("F"):
                opcode_categories[opcode] = "FPU_ARITHMETIC"

            # System Information and Random Number Generation
            elif opcode in ["PUSHF", "POPF", "CPUID", "RDTSC", "RDRAND", "RDSEED"]:
                opcode_categories[opcode] = "CPU_FEATURES"

            # Cryptography
            elif opcode.startswith("AES") or opcode.startswith("SHA"):
                opcode_categories[opcode] = "CRYPTOGRAPHIC"

            # Miscellaneous (including flag operations)
            else:
                opcode_categories[opcode] = "MISC"

        # Additional categorization for opcodes not in COMMON_OPCODES
        # This can be used in the normalize_opcode method

        # Store both maps as instance variables
        # self.opcode_categories = opcode_categories
        self.opcode_index = opcode_index

        return opcode_categories

    def is_simd_register(self, register):
        return register in self.sse_xmm