Neeta Pandey - RankMe

78 papers C 1Misc 1Journal 63Unranked 12

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	An Electronically Tunable Dual Flux-Controlled Floating Memristor Emulator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Navnit Kumar, Neeta Pandey, Manjeet Kumar, Manish Kumar, Shahram Minaei
2026	J	`jnl`	Compact design of MOSFET-only meminductor emulator and its application in chaos and neural spike generator. Integr. Anuj Kalra, Neeta Pandey, Shireesh Kumar Rai
2026	J	`jnl`	Memristor-Aided Dynamic Positive Feedback Source Coupled Logic. J. Circuits Syst. Comput. Shikha Mouria, Neeta Pandey, Kirti Gupta
2026	J	`jnl`	Novel Design Approach of Three-Input Logic Implementation in Positive Feedback Source Coupled Logic Style. J. Circuits Syst. Comput. Shikha Mouria, Kirti Gupta, Neeta Pandey
2025	J	`jnl`	A robust, low power and high speed radiation hardened 12T SRAM cell for space applications. Microelectron. J. Lokesh Soni, Neeta Pandey
2025	J	`jnl`	Frequency Compensation of Three-Stage Amplifier with Self-Cascode Structure and DTMOS Transistor with Active LHP Zero Circuit. J. Circuits Syst. Comput. Om Krishna Gupta, Neeta Pandey, Maneesha Gupta
2025	J	`jnl`	High-performance radiation hardened latch using Schmitt trigger. Integr. Niraj Kumar, Chaudhary Indra Kumar, Neeta Pandey
2025	J	`jnl`	Resistorless Realization of Three-Port Circulator using Operational Transconductance Amplifiers. J. Circuits Syst. Comput. Priyanka Gupta, Neeta Pandey, Rajeshwari Pandey
2025	J	`jnl`	Second generation current conveyor based capacitorless floating memristor emulator. Int. J. Circuit Theory Appl. Navnit Kumar, Manjeet Kumar, Neeta Pandey, Shahram Minaei
2025	J	`jnl`	Single Topology-Based Reconfigurable Positive and Negative Immittance Circuit and its Application as Multifunction Filter and Quadrature Oscillator. J. Circuits Syst. Comput. Navnit Kumar, Manjeet Kumar, Neeta Pandey
2024	J	`jnl`	A Single Bitline Highly Stable, Low Power With High Speed Half-Select Disturb Free 11T SRAM Cell. ACM Trans. Design Autom. Electr. Syst. Lokesh Soni, Neeta Pandey
2024	J	`jnl`	A low power Schmitt-trigger driven 10T SRAM Cell for high speed applications. Integr. Lokesh Soni, Neeta Pandey
2023	J	`jnl`	A Novel Chaotic System with Exponential Nonlinearity and its Adaptive Self-Synchronization: From Numerical Simulations to Circuit Implementation. J. Circuits Syst. Comput. Kriti Suneja, Neeta Pandey, Rajeshwari Pandey
2023	J	`jnl`	CCTA based four different pairs of mutually coupled circuit using single topology. Integr. Navnit Kumar, Manjeet Kumar, Neeta Pandey
2023	J	`jnl`	Electronically tunable positive and negative fractional order inductor circuit using single topology. Integr. Navnit Kumar, Manjeet Kumar, Neeta Pandey
2023	J	`jnl`	LDML: A Proposal to Reduce Leakage Power in DML Circuits. Wirel. Pers. Commun. Neetika Yadav, Neeta Pandey, Deva Nand
2023	J	`jnl`	Memristor-Based Architectures for PFSCL Circuit Realizations. Circuits Syst. Signal Process. Shikha, Neeta Pandey, Kirti Gupta
2023	J	`jnl`	Modeling of Dual- Metal Junctionless Accumulation-Mode cylindrical surrounding gate (DM-JAM-CSG) MOSFET for cryogenic temperature applications. Microelectron. J. Sumedha Gupta, Neeta Pandey, R. S. Gupta
2023	J	`jnl`	Modified Dual Mode Transmission Gate Diffusion Input Logic for Improving Energy Efficiency. J. Circuits Syst. Comput. Neetika Yadav, Neeta Pandey, Deva Nand
2023	J	`jnl`	PLC and SCADA based Real Time Monitoring and Train Control System for the Metro Railways Infrastructure. Wirel. Pers. Commun. Ishu Tomar, Indu Sreedevi, Neeta Pandey
2023	J	`jnl`	Process invariant Schmitt Trigger non-volatile 13T1M SRAM cell. Microelectron. J. Damyanti Singh, Neeta Pandey, Kirti Gupta
2023	J	`jnl`	Real Time Control System for Metro Railways Using PLC & SCADA. Intell. Autom. Soft Comput. Ishu Tomar, Indu Sreedevi, Neeta Pandey
2023	—	`conf`	Refining RNMC compensation for Three Stage Amplifier using DTMOS Transistor and FFVF. ICCCNT Om Krishna Gupta, Neeta Pandey, Maneesha Gupta
2022	J	`jnl`	A novel design of a 1 GHz phase locked loop with improved lock time for fast frequency acquisition. Int. J. Comput. Aided Eng. Technol. Monika Bhardwaj, Sujata Pandey, Neeta Pandey
2022	J	`jnl`	A novel read decoupled 8T1M nvSRAM cell for near threshold operation. Microelectron. J. Damyanti Singh, Kirti Gupta, Neeta Pandey
2022	J	`jnl`	Novel Pehlivan-Uyarŏglu Chaotic System Variants and their CFOA Based Realization. J. Circuits Syst. Comput. Kriti Suneja, Neeta Pandey, Rajeshwari Pandey
2022	C	`conf`	OTA Based Fractional-Order Oscillator With Controlled Phase Difference. ISCAS Garima Varshney, Neeta Pandey, Rajeshwari Pandey
2022	J	`jnl`	On improving the performance of dynamic positive-feedback source-coupled logic (D-PFSCL) through inclusion of transmission gates. Microprocess. Microsystems Ranjana Sivaram, Kirti Gupta, Neeta Pandey
2021	J	`jnl`	A data-independent 9T SRAM cell with enhanced ION/IOFF ratio and RBL voltage swing in near threshold and sub-threshold region. Int. J. Circuit Theory Appl. Monica Gupta, Kirti Gupta, Neeta Pandey
2021	J	`jnl`	A novel PVT-variation-tolerant Schmitt-trigger-based 12T SRAM cell with improved write ability and high ION/IOFF ratio in sub-threshold region. Int. J. Circuit Theory Appl. Monica Gupta, Kirti Gupta, Neeta Pandey
2021	J	`jnl`	A novel design for voltage inverting metamutator and its applications. Microelectron. J. R. Arundeepakvel, Jatin, Parth Khatter, Neeta Pandey, Shahram Minaei
2021	J	`jnl`	Clock Aligned Input Adiabatic Logic. Microelectron. J. Aditya S. Kumar, Sagar Jain, Neeta Pandey
2021	J	`jnl`	Comparative Analysis of the Design Techniques for Low Leakage SRAMs at 32nm. Microprocess. Microsystems Monica Gupta, Kirti Gupta, Neeta Pandey
2021	J	`jnl`	Generalization of shadow filters in fractional domain. Int. J. Circuit Theory Appl. Garima Varshney, Neeta Pandey, Rajeshwari Pandey
2021	J	`jnl`	Leakage reduction in dual mode logic through gated leakage transistors. Microprocess. Microsystems Neetika Yadav, Neeta Pandey, Deva Nand
2021	J	`jnl`	Unified floating immittance emulator based on CCTA. Microelectron. J. Navnit Kumar, Manjeet Kumar, Neeta Pandey
2020	J	`jnl`	A low power subthreshold Schmitt Trigger based 12T SRAM bit cell with process-variation-tolerant write-ability. Microelectron. J. Prakhar Sharma, Shourya Gupta, Kirti Gupta, Neeta Pandey
2020	J	`jnl`	A new realization scheme for dynamic PFSCL style. Integr. Ranjana Sivaram, Kirti Gupta, Neeta Pandey
2020	—	`book`	Model and Design of Improved Current Mode Logic Gates - Differential and Single-ended Kirti Gupta, Neeta Pandey, Maneesha Gupta
2019	—	`conf`	Hardware/Software Co-Design of a High-Speed Othello Solver. MWSCAS Pranav Gangwar, Satvik Maurya, Shubham Garg, Sakshi Goyal, Aditya S. Kumar, Preyesh Dalmia, Neeta Pandey
2019	J	`jnl`	Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Shourya Gupta, Kirti Gupta, Benton H. Calhoun, Neeta Pandey
2019	J	`jnl`	New sinusoidal oscillator configurations using operational transresistance amplifier. Int. J. Circuit Theory Appl. Gurumurthy Komanapalli, Rajeshwari Pandey, Neeta Pandey
2019	—	`conf`	Novel Control Unit Design for a High-Speed SHA-3 Architecture. MWSCAS Pranav Gangwar, Neeta Pandey, Rajeshwari Pandey
2019	J	`jnl`	Operational Transresistance Amplifier Based Wienbridge Oscillator and Its Harmonic Analysis. Wirel. Pers. Commun. Gurumurthy Komanapalli, Rajeshwari Pandey, Neeta Pandey
2019	J	`jnl`	Programmable CCCII: reliability analysis and design methodology. IET Circuits Devices Syst. Manoj Kumar Tiwari, Neeta Pandey, Sajal K. Paul, Saiyid Mohammad Irshad Rizvi
2019	J	`jnl`	Realization of Resistorless and Electronically Tunable Inverse Filters Using VDTA. J. Circuits Syst. Comput. Praveen Kumar, Neeta Pandey, Sajal K. Paul
2018	—	`conf`	Design of an SCL logic based Current Comparator. MWSCAS Veepsa Bhatia, Neeta Pandey, Sri Ranjani Prasanthi
2018	—	`conf`	MCML Dynamic Register Design. MWSCAS Neeta Pandey, Kirti Gupta, Bharat Choudhary
2018	Misc	`conf`	Novel High Speed Vedic Multiplier Proposal Incorporating Adder Based on Quaternary Signed Digit Number System. VLSID Preyesh Dalmia, Vikas, Abhinav Parashar, Akshi Tomar, Neeta Pandey
2018	—	`conf`	OTRA Based Log and Antilog Amplifiers. MWSCAS Rajeshwari Pandey, Neeta Pandey
2018	J	`jnl`	Pentavariate V IEEE Trans. Circuits Syst. I Regul. Pap. Shourya Gupta, Kirti Gupta, Neeta Pandey
2017	J	`jnl`	A 32-nm Subthreshold 7T SRAM Bit Cell With Read Assist. IEEE Trans. Very Large Scale Integr. Syst. Shourya Gupta, Kirti Gupta, Neeta Pandey
2017	—	`conf`	Implementation and Performance Comparison of a Four-Bit Ripple-Carry Adder Using Different MOS Current Mode Logic Topologies. ICCSA (6) Naman Saxena, Shruti Dutta, Neeta Pandey, Kirti Gupta
2017	J	`jnl`	Modified Tang and Pun's Current Comparator and Its Application to Full Flash and Two-Step Flash Current Mode ADCs. J. Electr. Comput. Eng. Veepsa Bhatia, Neeta Pandey
2017	J	`jnl`	New Sleep-Based PFSCL Tri-State Inverter/Buffer Topologies. J. Circuits Syst. Comput. Neeta Pandey, Bharat Choudhary, Kirti Gupta, Ankit Mittal
2017	J	`jnl`	On Improving the Performance of Dynamic DCVSL Circuits. J. Electr. Comput. Eng. Pratibha Bajpai, Neeta Pandey, Kirti Gupta, Shrey Bagga, Jeebananda Panda
2016	—	`conf`	A Novel Bulk Drain Connected 6T SRAM Cell. ICACDS Shobhit Kareer, Anchit Kumar, Kirti Gupta, Neeta Pandey
2016	—	`conf`	A Novel Ultra Low Power Current Comparator. ICACDS Veepsa Bhatia, Neeta Pandey
2016	J	`jnl`	Generalised operational floating current conveyor based instrumentation amplifier. IET Circuits Devices Syst. Neeta Pandey, Deva Nand, Rajeshwari Pandey
2016	J	`jnl`	MOS current mode logic exclusive-OR gate using multi-threshold triple-tail cells. Microelectron. J. Neeta Pandey, Kirti Gupta, Garima Bhatia, Bharat Choudhary
2016	J	`jnl`	New Proposal for MCML Based Three-Input Logic Implementation. VLSI Design Neeta Pandey, Kirti Gupta, Bharat Choudhary
2016	—	`conf`	Universal biquadratic filter using Operational Floating Current Conveyor (OFCC). ICM Divyesh Sachan, Deva Nand, Neeta Pandey
2015	J	`jnl`	Approach for third order quadrature oscillator realisation. IET Circuits Devices Syst. Neeta Pandey, Rajeshwari Pandey
2014	J	`jnl`	An efficient triple-tail cell based PFSCL D latch. Microelectron. J. Neeta Pandey, Kirti Gupta, Maneesha Gupta
2014	J	`jnl`	Novel grounded inductance simulator using single OTRA. Int. J. Circuit Theory Appl. Rajeshwari Pandey, Neeta Pandey, Sajal K. Paul, Ajay Singh, B. Sriram, Kaushlendra Trivedi
2013	J	`jnl`	Analysis and design of MOS current mode logic exclusive-OR gate using triple-tail cells. Microelectron. J. Kirti Gupta, Neeta Pandey, Maneesha Gupta
2013	J	`jnl`	Mixed Mode Universal filter. J. Circuits Syst. Comput. Neeta Pandey, Sajal K. Paul
2012	—	`conf`	An expandable current-mode ADC with power optimization technique. RAIT Veepsa Bhatia, Neeta Pandey, Asok Bhattacharyya
2011	J	`jnl`	Differential Difference Current Conveyor Transconductance Amplifier: A New Analog Building Block for Signal Processing. J. Electr. Comput. Eng. Neeta Pandey, Sajal K. Paul
2011	J	`jnl`	MO-CCCCTA-Based Floating Positive and Negative Inductors and Their Applications. J. Electr. Comput. Eng. Neeta Pandey, Rishik Bazaz, Rahul Manocha
2011	J	`jnl`	New Low-Power Tristate Circuits in Positive Feedback Source-Coupled Logic. J. Electr. Comput. Eng. Kirti Gupta, Ranjana Sridhar, Jaya Chaudhary, Neeta Pandey, Maneesha Gupta
2011	J	`jnl`	New Topologies of Lossless Grounded Inductor Using OTRA. J. Electr. Comput. Eng. Rajeshwari Pandey, Neeta Pandey, Sajal K. Paul, Aditya Singh, B. Sriram, Kaushalendra Trivedi
2011	J	`jnl`	Operational Transresistance Amplifier-Based Multiphase Sinusoidal Oscillators. J. Electr. Comput. Eng. Rajeshwari Pandey, Neeta Pandey, Mayank Bothra, Sajal K. Paul
2011	J	`jnl`	Single CDTA-Based Current Mode All-Pass Filter and Its Applications. J. Electr. Comput. Eng. Neeta Pandey, Sajal K. Paul
2010	J	`jnl`	SIMO Transadmittance Mode Active-C Universal Filter. Circuits Syst. Neeta Pandey, Sajal K. Paul
2006	J	`jnl`	A new mixed mode biquad using reduced number of active and passive elements. IEICE Electron. Express Neeta Pandey, Sajal K. Paul, Asok Bhattacharyya, S. B. Jain
2005	J	`jnl`	A novel current controlled current mode universal filter: SITO approach. IEICE Electron. Express Neeta Pandey, Sajal K. Paul, Asok Bhattacharyya, S. B. Jain
2005	—	`conf`	An insensitive current mode universal biquad: multi-input multi-output. ISCAS (4) Neeta Pandey, Sajal K. Paul, Asok Bhattacharyya