Navin Srivastava

14 papers A* 3A 3C 1Journal 4Unranked 3

Year	Rank	Type	Title / Venue / Authors
2012	J	`jnl`	Fast High-Frequency Impedance Extraction of Horizontal Interconnects and Inductors in 3-D ICs With Multiple Substrates. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chuan Xu, Navin Srivastava, Roberto Suaya, Kaustav Banerjee
2010	J	`jnl`	Corrections to "Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate" [Jul 09 1047-1060]. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Navin Srivastava, Chuan Xu, Roberto Suaya, Kaustav Banerjee
2010	A	`conf`	Efficient 3D high-frequency impedance extraction for general interconnects and inductors above a layered substrate. DATE Navin Srivastava, Roberto Suaya, Kaustav Banerjee
2009	J	`jnl`	Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Navin Srivastava, Roberto Suaya, Kaustav Banerjee
2008	A	`conf`	High-Frequency Mutual Impedance Extraction of VLSI Interconnects In the Presence of a Multi-layer Conducting Substrate. DATE Navin Srivastava, Roberto Suaya, Kaustav Banerjee
2007	J	`jnl`	3D Integration for Introspection. IEEE Micro Shashidhar Mysore, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Kaustav Banerjee, Timothy Sherwood
2006	A*	`conf`	A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy. DAC Gian Luca Loi, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Timothy Sherwood, Kaustav Banerjee
2006	A*	`conf`	Are carbon nanotubes the future of VLSI interconnections? DAC Kaustav Banerjee, Navin Srivastava
2006	—	`conf`	Can Carbon Nanotubes Extend the Lifetime of On-Chip Electrical Interconnections? Nano-Net Kaustav Banerjee, Sungjun Im, Navin Srivastava
2006	—	`conf`	Electrothermal engineering in the nanometer era: from devices and interconnects to circuits and systems. ASP-DAC Kaustav Banerjee, Sheng-Chih Lin, Navin Srivastava
2006	A*	`conf`	Introspective 3D chips. ASPLOS Shashidhar Mysore, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Kaustav Banerjee, Timothy Sherwood
2005	C	`conf`	A Thermally-Aware Methodology for Design-Specific Optimization of Supply and Threshold Voltages in Nanometer Scale ICs. ICCD Sheng-Chih Lin, Navin Srivastava, Kaustav Banerjee
2005	—	`conf`	Impact of On-chip Inductance on Power Distribution Network Design for Nanometer Scale Integrated Circuits. ISQED Navin Srivastava, Xiaoning Qi, Kaustav Banerjee
2005	A	`conf`	Performance analysis of carbon nanotube interconnects for VLSI applications. ICCAD Navin Srivastava, Kaustav Banerjee