Naveen Suda

30 papers A* 2A 2B 1C 2Misc 1Journal 19Unranked 3
YearRankTypeTitle / Venue / Authors
2026 J jnl
MobileLLM-Flash: Latency-Guided On-Device LLM Design for Industry Scale Deployment.
CoRR
Hanxian Huang, Igor Fedorov, Andrey Gromov, Bernard Beckerman, Naveen Suda, David Eriksson, Maximilian Balandat, Rylan Conway, Patrick Huber, Chinnadhurai Sankar, Ayushi Dalmia, Zechun Liu, Lemeng Wu, Tarek Elgamal, Adithya Sagar, Vikas Chandra, Raghuraman Krishnamoorthi
2025 J jnl
MobileLLM-Pro Technical Report.
CoRR
Patrick Huber, Ernie Chang, Wei Wen, Igor Fedorov, Tarek Elgamal, Hanxian Huang, Naveen Suda, Chinnadhurai Sankar, Vish Vogeti, Yanghan Wang, Alex Gladkov, Kai Sheng Tai, Abdelrahman Elogeel, Tarek Hefny, Vikas Chandra, Ahmed Aly, Anuj Kumar, Raghuraman Krishnamoorthi, Adithya Sagar
2024 J jnl
Llama Guard 3-1B-INT4: Compact and Efficient Safeguard for Human-AI Conversations.
CoRR
Igor Fedorov, Kate Plawiak, Lemeng Wu, Tarek Elgamal, Naveen Suda, Eric Smith, Hongyuan Zhan, Jianfeng Chi, Yuriy Hulovatyy, Kimish Patel, Zechun Liu, Changsheng Zhao, Yangyang Shi, Tijmen Blankevoort, Mahesh Pasupuleti, Bilge Soran, Zacharie Delpierre Coudert, Rachad Alao, Raghuraman Krishnamoorthi, Vikas Chandra
2024 A* conf
Towards Open-World Gesture Recognition.
ISMAR
Junxiao Shen, Matthias De Lange, Xuhai Xu, Enmin Zhou, Ran Tan, Naveen Suda, Maciej Lazarewicz, Per Ola Kristensson, Amy Karlson, Evan Strasnick
2024 J jnl
Towards Open-World Gesture Recognition.
CoRR
Junxiao Shen, Matthias De Lange, Xuhai Orson Xu, Enmin Zhou, Ran Tan, Naveen Suda, Maciej Lazarewicz, Per Ola Kristensson, Amy Karlson, Evan Strasnick
2022 — conf
Collapsible Linear Blocks for Super-Efficient Super Resolution.
MLSys
Kartikeya Bhardwaj, Milos Milosavljevic, Liam O'Neil, Dibakar Gope, Ramon Matas Navarro, Alex Chalfin, Naveen Suda, Lingchuan Meng, Danny Loh
2021 J jnl
Collapsible Linear Blocks for Super-Efficient Super Resolution.
CoRR
Kartikeya Bhardwaj, Milos Milosavljevic, Alex Chalfin, Naveen Suda, Liam O'Neil, Dibakar Gope, Lingchuan Meng, Ramon Matas Navarro, Danny Loh
2021 J jnl
EdgeAl: A Vision for Deep Learning in the IoT Era.
IEEE Des. Test
Kartikeya Bhardwaj, Naveen Suda, Radu Marculescu
2019 J jnl
Dream Distillation: A Data-Independent Model Compression Framework.
CoRR
Kartikeya Bhardwaj, Naveen Suda, Radu Marculescu
2019 J jnl
EdgeAI: A Vision for Deep Learning in IoT Era.
CoRR
Kartikeya Bhardwaj, Naveen Suda, Radu Marculescu
2019 Misc conf
SenseHAR: a robust virtual activity sensor for smartphones and wearables.
SenSys
Jeya Vikranth Jeyakumar, Liangzhen Lai, Naveen Suda, Mani B. Srivastava
2018 J jnl
ALAMO: FPGA acceleration of deep learning algorithms with a modularized RTL compiler.
Integr.
Yufei Ma, Naveen Suda, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo
2018 A* conf
Bit Fusion: Bit-Level Dynamically Composable Architecture for Accelerating Deep Neural Network.
ISCA
Hardik Sharma, Jongse Park, Naveen Suda, Liangzhen Lai, Benson Chau, Vikas Chandra, Hadi Esmaeilzadeh
2018 J jnl
CMSIS-NN: Efficient Neural Network Kernels for Arm Cortex-M CPUs.
CoRR
Liangzhen Lai, Naveen Suda, Vikas Chandra
2018 A conf
Enabling deep learning at the IoT edge.
ICCAD
Liangzhen Lai, Naveen Suda
2018 J jnl
Federated Learning with Non-IID Data.
CoRR
Yue Zhao, Meng Li, Liangzhen Lai, Naveen Suda, Damon Civin, Vikas Chandra
2018 J jnl
Not All Ops Are Created Equal!
CoRR
Liangzhen Lai, Naveen Suda, Vikas Chandra
2018 J jnl
Rethinking Machine Learning Development and Deployment for Edge Devices.
CoRR
Liangzhen Lai, Naveen Suda
2017 — conf
A real-time 17-scale object detection accelerator with adaptive 2000-stage classification in 65nm CMOS.
ASP-DAC
Minkyu Kim, Abinash Mohanty, Deepak Kadetotad, Naveen Suda, Luning Wei, Pooja Saseendran, Xiaofei He, Yu Cao, Jae-sun Seo
2017 C conf
A real-time 17-scale object detection accelerator with adaptive 2000-stage classification in 65nm CMOS.
ISCAS
Minkyu Kim, Abinash Mohanty, Deepak Kadetotad, Naveen Suda, Luning Wei, Pooja Saseendran, Xiaofei He, Yu Cao, Jae-sun Seo
2017 J jnl
Bit Fusion: Bit-Level Dynamically Composable Architecture for Accelerating Deep Neural Networks.
CoRR
Hardik Sharma, Jongse Park, Naveen Suda, Liangzhen Lai, Benson Chau, Joon Kyung Kim, Vikas Chandra, Hadi Esmaeilzadeh
2017 J jnl
Deep Convolutional Neural Network Inference with Floating-point Weights and Fixed-point Activations.
CoRR
Liangzhen Lai, Naveen Suda, Vikas Chandra
2017 J jnl
Hello Edge: Keyword Spotting on Microcontrollers.
CoRR
Yundong Zhang, Naveen Suda, Liangzhen Lai, Vikas Chandra
2017 J jnl
PrivyNet: A Flexible Framework for Privacy-Preserving Deep Neural Network Training with A Fine-Grained Privacy Control.
CoRR
Meng Li, Liangzhen Lai, Naveen Suda, Vikas Chandra, David Z. Pan
2016 J jnl
A 65 nm Programmable ANalog Device Array (PANDA) for Analog Circuit Emulation.
IEEE Trans. Circuits Syst. I Regul. Pap.
Naveen Suda, Jounghyuk Suh, Nagib Hakim, Yu Cao, Bertan Bakkaloglu
2016 C conf
High-performance face detection with CPU-FPGA acceleration.
ISCAS
Abinash Mohanty, Naveen Suda, Minkyu Kim, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao
2016 B conf
Scalable and modularized RTL compilation of Convolutional Neural Networks onto FPGA.
FPL
Yufei Ma, Naveen Suda, Yu Cao, Jae-sun Seo, Sarma B. K. Vrudhula
2016 A conf
Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks.
FPGA
Naveen Suda, Vikas Chandra, Ganesh Dasika, Abinash Mohanty, Yufei Ma, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao
2015 — conf
A 14.8μVRMS integrated noise output capacitor-less low dropout regulator with a switched-RC bandgap reference.
CICC
Raveesh Magod, Naveen Suda, Vadim Ivanov, Ravi Balasingam, Bertan Bakkaloglu
2013 J jnl
Programmable ANalog Device Array (PANDA): A Methodology for Transistor-Level Analog Emulation.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jounghyuk Suh, Naveen Suda, Cheng Xu, Nagib Hakim, Yu Cao, Bertan Bakkaloglu