Naveen Muralimanohar

43 papers A* 16A 8B 2C 2Misc 1Journal 11

Year	Rank	Type	Title / Venue / Authors
2018	J	`jnl`	Newton: Gravitating Towards the Physical Limits of Crossbar Acceleration. CoRR Anirban Nag, Ali Shafiee, Rajeev Balasubramonian, Vivek Srikumar, Naveen Muralimanohar
2018	J	`jnl`	Newton: Gravitating Towards the Physical Limits of Crossbar Acceleration. IEEE Micro Anirban Nag, Rajeev Balasubramonian, Vivek Srikumar, Ross Walker, Ali Shafiee, John Paul Strachan, Naveen Muralimanohar
2017	J	`jnl`	CACTI 7: New Tools for Interconnect Exploration in Innovative Off-Chip Memories. ACM Trans. Archit. Code Optim. Rajeev Balasubramonian, Andrew B. Kahng, Naveen Muralimanohar, Ali Shafiee, Vaishnav Srinivas
2016	C	`conf`	Enabling technologies for memory compression: Metadata, mapping, and prediction. ICCD Arjun Deb, Paolo Faraboschi, Ali Shafiee, Naveen Muralimanohar, Rajeev Balasubramonian, Robert Schreiber
2016	A*	`conf`	ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars. ISCA Ali Shafiee, Anirban Nag, Naveen Muralimanohar, Rajeev Balasubramonian, John Paul Strachan, Miao Hu, R. Stanley Williams, Vivek Srikumar
2016	J	`jnl`	Near-Memory Data Services. IEEE Micro Babak Falsafi, Mircea Stan, Kevin Skadron, Nuwan Jayasena, Yunji Chen, Jinhua Tao, Ravi Nair, Jaime H. Moreno, Naveen Muralimanohar, Karthikeyan Sankaralingam, Cristian Estan
2015	J	`jnl`	CACTI-IO: CACTI With OFF-Chip Power-Area-Timing Models. IEEE Trans. Very Large Scale Integr. Syst. Norman P. Jouppi, Andrew B. Kahng, Naveen Muralimanohar, Vaishnav Srinivas
2015	A	`conf`	History-Assisted Adaptive-Granularity Caches (HAAG$) for High Performance 3D DRAM Architectures. ICS Ke Chen, Sheng Li, Jung Ho Ahn, Naveen Muralimanohar, Jishen Zhao, Cong Xu, Seongil O, Yuan Xie, Jay B. Brockman, Norman P. Jouppi
2015	C	`conf`	Improving memristor memory with sneak current sharing. ICCD Manjunath Shevgoor, Naveen Muralimanohar, Rajeev Balasubramonian, Yoocharn Jeon
2015	A*	`conf`	Overcoming the challenges of crossbar resistive memory architectures. HPCA Cong Xu, Dimin Niu, Naveen Muralimanohar, Rajeev Balasubramonian, Tao Zhang, Shimeng Yu, Yuan Xie
2014	J	`jnl`	Efficient Data Mapping and Buffering Techniques for Multilevel Cell Phase-Change Memories. ACM Trans. Archit. Code Optim. HanBin Yoon, Justin Meza, Naveen Muralimanohar, Norman P. Jouppi, Onur Mutlu
2013	A	`conf`	Design of cross-point metal-oxide ReRAM emphasizing reliability and cost. ICCAD Dimin Niu, Cong Xu, Naveen Muralimanohar, Norman P. Jouppi, Yuan Xie
2013	A*	`conf`	Understanding the trade-offs in multi-level cell ReRAM memory design. DAC Cong Xu, Dimin Niu, Naveen Muralimanohar, Norman P. Jouppi, Yuan Xie
2012	A*	`conf`	BOOM: Enabling mobile memory based low-power server DIMMs. ISCA Doe Hyun Yoon, Jichuan Chang, Naveen Muralimanohar, Parthasarathy Ranganathan
2012	A	`conf`	CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory. DATE Ke Chen, Sheng Li, Naveen Muralimanohar, Jung Ho Ahn, Jay B. Brockman, Norman P. Jouppi
2012	A	`conf`	CACTI-IO: CACTI with off-chip power-area-timing models. ICCAD Norman P. Jouppi, Andrew B. Kahng, Naveen Muralimanohar, Vaishnav Srinivas
2012	A	`conf`	Design trade-offs for high density cross-point resistive memory. ISLPED Dimin Niu, Cong Xu, Naveen Muralimanohar, Norman P. Jouppi, Yuan Xie
2012	J	`jnl`	Free-p: A Practical End-to-End Nonvolatile Memory Protection Mechanism. IEEE Micro Doe Hyun Yoon, Naveen Muralimanohar, Jichuan Chang, Parthasarathy Ranganathan, Norman P. Jouppi, Mattan Erez
2012	A*	`conf`	LOT-ECC: Localized and tiered reliability mechanisms for commodity memory systems. ISCA Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi
2012	J	`jnl`	Optical High Radix Switch Design. IEEE Micro Nathan L. Binkert, Al Davis, Norman P. Jouppi, Moray McLaren, Naveen Muralimanohar, Robert Schreiber, Jung Ho Ahn
2012	A*	`conf`	Staged Reads: Mitigating the impact of DRAM writes on DRAM reads. HPCA Niladrish Chatterjee, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi
2011	—	`ch.`	CMOS Nanophotonics: Technology, System Implications, and a CMP Case Study. Low Power Networks-on-Chip Jung Ho Ahn, Raymond G. Beausoleil, Nathan L. Binkert, Al Davis, Marco Fiorentino, Norman P. Jouppi, Moray McLaren, Matteo Monchiero, Naveen Muralimanohar, Robert Schreiber, Dana Vantrease
2011	A*	`conf`	Combining memory and a controller with photonics through 3D-stacking to enable scalable and energy-efficient systems. ISCA Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi
2011	A*	`conf`	FREE-p: Protecting non-volatile memory against both hard and soft errors. HPCA Doe Hyun Yoon, Naveen Muralimanohar, Jichuan Chang, Parthasarathy Ranganathan, Norman P. Jouppi, Mattan Erez
2011	J	`jnl`	Hybrid checkpointing using emerging nonvolatile memories for future exascale systems. ACM Trans. Archit. Code Optim. Xiangyu Dong, Yuan Xie, Naveen Muralimanohar, Norman P. Jouppi
2011	—	`book`	Multi-Core Cache Hierarchies Rajeev Balasubramonian, Norman P. Jouppi, Naveen Muralimanohar
2011	A	`conf`	System implications of memory reliability in exascale computing. SC Sheng Li, Ke Chen, Ming-yu Hsieh, Naveen Muralimanohar, Chad D. Kersey, Jay B. Brockman, Arun F. Rodrigues, Norman P. Jouppi
2011	A*	`conf`	The role of optics in future high radix switch design. ISCA Nathan L. Binkert, Al Davis, Norman P. Jouppi, Moray McLaren, Naveen Muralimanohar, Robert Schreiber, Jung Ho Ahn
2010	A*	`conf`	Rethinking DRAM design and organization for energy-constrained multi-cores. ISCA Aniruddha N. Udipi, Naveen Muralimanohar, Niladrish Chatterjee, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi
2010	A	`conf`	Simple but Effective Heterogeneous Main Memory with On-Chip Memory Controller Support. SC Xiangyu Dong, Yuan Xie, Naveen Muralimanohar, Norman P. Jouppi
2010	A*	`conf`	Towards scalable, energy-efficient, bus-based on-chip networks. HPCA Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian
2009	A	`conf`	Leveraging 3D PCRAM technologies to reduce checkpoint overhead for future exascale systems. SC Xiangyu Dong, Naveen Muralimanohar, Norman P. Jouppi, Richard Kaufmann, Yuan Xie
2009	Misc	`conf`	Non-uniform power access in large caches with low-swing wires. HiPC Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian
2009	A*	`conf`	Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy. HPCA Niti Madan, Li Zhao, Naveen Muralimanohar, Aniruddha N. Udipi, Rajeev Balasubramonian, Ravishankar R. Iyer, Srihari Makineni, Donald Newell
2009	—	`—`	Wire Aware Cache Architecture. Naveen Muralimanohar
2008	J	`jnl`	Architecting Efficient Interconnects for Large Caches with CACTI 6.0. IEEE Micro Naveen Muralimanohar, Rajeev Balasubramonian, Norman P. Jouppi
2008	B	`conf`	Scalable and reliable communication for hardware transactional memory. PACT Seth H. Pugsley, Manu Awasthi, Niti Madan, Naveen Muralimanohar, Rajeev Balasubramonian
2007	A*	`conf`	Interconnect design considerations for large NUCA caches. ISCA Naveen Muralimanohar, Rajeev Balasubramonian
2007	A*	`conf`	Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0. MICRO Naveen Muralimanohar, Rajeev Balasubramonian, Norman P. Jouppi
2006	A*	`conf`	Interconnect-Aware Coherence Protocols for Chip Multiprocessors. ISCA Liqun Cheng, Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian, John B. Carter
2006	J	`jnl`	Leveraging Wire Properties at the Microarchitecture Level. IEEE Micro Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Liqun Cheng, John B. Carter
2006	B	`conf`	Power efficient resource scaling in partitioned architectures through dynamic heterogeneity. ISPASS Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian
2005	A*	`conf`	Microarchitectural Wire Management for Performance and Power in Partitioned Architectures. HPCA Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Venkatanand Venkatachalapathy