Naveen Kadayinti

12 papers C 2Misc 2Journal 6Unranked 2

Year	Rank	Type	Title / Venue / Authors
2024	—	`conf`	TRNG Based on Multiple Entropy Sources Using CTDSM. APCCAS Apurv Pandey, Naveen Kadayinti
2023	—	`conf`	Mismatch Tolerant Negative Conductance Load Tuning for High Gain OTAs. APCCAS Mayur S. Marinaik, Naveen Kadayinti
2022	C	`conf`	A True Time Delay Element using Cascaded Variable Bandwidth All Pass Filters. ISCAS Mayur S. Marinaik, Ganga K. Maheshwarappa, Naveen Kadayinti
2018	J	`jnl`	Measurements of the effect of jitter on the performance of clock retiming circuits for on-chip interconnects. Microelectron. J. Naveen Kadayinti, Maryam Shojaei Baghini, Dinesh Kumar Sharma
2017	Misc	`conf`	A Clock Retiming Circuit for Repeaterless Low Swing On-Chip Interconnects. VLSID Naveen Kadayinti, Maryam Shojaei Baghini, Dinesh Kumar Sharma
2017	Misc	`conf`	Clock Skew Measurement Using an All-Digital Sigma-Delta Time to Digital Converter. VLSID Mahadev Govind Shirwaikar, Naveen Kadayinti, Dinesh Kumar Sharma
2017	J	`jnl`	Sense Amplifier Comparator with Offset Correction for Decision Feedback Equalization based Receivers. CoRR Naveen Kadayinti, Dinesh Kumar Sharma
2017	J	`jnl`	Sense amplifier comparator with offset correction for decision feedback equalization based receivers. Microelectron. J. Naveen Kadayinti, Dinesh Kumar Sharma
2017	C	`conf`	Settling time of mesochronous clock re-timing circuits in the presence of timing jitter. ISCAS Naveen Kadayinti, Amitalok J. Budkuley, Dinesh Kumar Sharma
2016	J	`jnl`	Settling Time of Mesochronous Clock Retiming Circuits for Low Swing Interconnects. CoRR Naveen Kadayinti, Amitalok J. Budkuley, Dinesh Kumar Sharma
2015	J	`jnl`	A Clock Synchronizer for Repeaterless Low Swing On-Chip Links. CoRR Naveen Kadayinti, Maryam Shojaei Baghini, Dinesh Kumar Sharma
2015	J	`jnl`	Testable Design of Repeaterless Low Swing On-Chip Interconnect. CoRR Naveen Kadayinti, Dinesh Kumar Sharma