Naveed A. Sherwani

51 papers A* 9A 6C 6Misc 7Journal 11Unranked 10

Year	Rank	Type	Title / Venue / Authors
2009	—	`conf`	Dreams, Plans, and Journey of Reaching Perfect Predictability and Reliability in ASICs. DFT Naveed A. Sherwani
2005	A*	`conf`	DFM rules! DAC Naveed A. Sherwani, Susan Lippincott Mack, Alex Alexanian, Premal Buch, Carlo Guardiani, Harold Lehon, Peter Rabkin, Atul Sharan
2003	A*	`conf`	COT - customer owned trouble. DAC Robert Dahlberg, Shishpal Rawat, Jen Bernier, Gina Gloski, Aurangzeb Khan, Kaushik Patel, Paul Ruddy, Naveed A. Sherwani, Ronnie Vasishta
2003	J	`jnl`	Integrated floorplanning with buffer/channel insertion for bus-based designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Faran Rafiq, Malgorzata Chrzanowska-Jeske, Hannah Honghua Yang, Marcin Jeske, Naveed A. Sherwani
2002	—	`conf`	Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs. ISPD Faran Rafiq, Malgorzata Chrzanowska-Jeske, Hannah Honghua Yang, Naveed A. Sherwani
2000	J	`jnl`	EDA challenges facing future microprocessor design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. T. Karn, Shishpal Rawat, Desmond Kirkpatrick, Rabindra K. Roy, Gregory S. Spirakis, Naveed A. Sherwani, Craig Peterson
2000	J	`jnl`	On the use of flexible, rectilinear blocks to obtain minimum-area floorplans in mixed block and cell designs. ACM Trans. Design Autom. Electr. Syst. Dinesh P. Mehta, Naveed A. Sherwani
2000	—	`conf`	The bottom-10 problems in EDA (panel session (title only)). ISPD Naveed A. Sherwani
1999	A	`conf`	Integrated floorplanning and interconnect planning. ICCAD Hung-Ming Chen, Hai Zhou, Fung Yu Young, D. F. Wong, Hannah Honghua Yang, Naveed A. Sherwani
1999	—	`conf`	SRC physical design top ten problem. ISPD Jeff Parkhurst, Naveed A. Sherwani, Sury Maturi, Dana Ahrams, Eli Chiprout
1998	Misc	`conf`	Embedded Tutorial: Layout Driven Synthesis or Synthesis Driven Layout. VLSI Design Naveed A. Sherwani, Prashant Sawkar
1997	Misc	`conf`	T3: Physical Design. VLSI Design Dinesh P. Mehta, Naveed A. Sherwani, A. Bariya
1996	—	`conf`	A Minimum-Area Floorplanning Algorithm for MBC Designs. Great Lakes Symposium on VLSI Dinesh P. Mehta, Naveed A. Sherwani
1996	J	`jnl`	Optimal algorithms for planar over-the-cell routing problems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Srinivasa R. Danda, Xiaolin Liu, Sreekrishna Madhwapathy, Anand Panyam, Naveed A. Sherwani, Ioannis G. Tollis
1995	—	`conf`	OPRON: a new approach to planar OTC routing. Great Lakes Symposium on VLSI Srinivasa R. Danda, Sreekrishna Madhwapathy, Naveed A. Sherwani, Aman Sureka
1995	Misc	`conf`	Optimal algorithms for planar over-the-cell routing in the presence of obstacles. VLSI Design Srinivasa R. Danda, Sreekrishna Madhwapathy, Naveed A. Sherwani
1994	C	`conf`	A Hierarchical Approach to Clock Routing in High Performance Systems. ISCAS Wasim Khan, Sreekrishna Madhwapathy, Naveed A. Sherwani
1994	A*	`conf`	A Unified Approach to Multilayer Over-the-Cell Routing. DAC Sreekrishna Madhwapathy, Naveed A. Sherwani, Siddharth Bhingarde, Anand Panyam
1994	A*	`conf`	Algorithmic Aspects of Three Dimensional MCM Routing. DAC Qiong Yu, Sandeep Badida, Naveed A. Sherwani
1994	C	`conf`	An Efficient Four Layer Over-the-Cell Router. ISCAS Sreekrishna Madhwapathy, Naveed A. Sherwani, Siddharth Bhingarde, Anand Panyam
1994	—	`conf`	An optimal algorithm for maximum two planar subset problem [VLSI layout]. Great Lakes Symposium on VLSI Anand Panyam, Srinivasa R. Danda, Sreekrishna Madhwapathy, Naveed A. Sherwani
1994	C	`conf`	Comparative Analysis of New CMOS Leaf Cells for OTC Routing. ISCAS Pramod Anne, Aditya Reddy, Naveed A. Sherwani, Anand Panyam, Siddharth Bhingarde
1994	—	`conf`	Floorplanning for mixed macro block and standard cell designs. Great Lakes Symposium on VLSI Arun Shanbhag, Srinivasa R. Danda, Naveed A. Sherwani
1994	Misc	`conf`	High Performance Over-the-Cell Routing. VLSI Design Jim E. Crenshaw, Spyros Tragoudas, Naveed A. Sherwani
1994	J	`jnl`	Incomplete hypercubes: Algorithms and embeddings. J. Supercomput. Alfred J. Boals, Ajay K. Gupta, Naveed A. Sherwani
1994	Misc	`conf`	Over-the-Cell Routing Algorithms for Industrial Cell Models. VLSI Design Siddharth Bhingarde, Rafay Khawaja, Anand Panyam, Naveed A. Sherwani
1993	Misc	`conf`	A Provably Good Algorithm for VLSI Design Jason Cong, Moazzem Hossain, Naveed A. Sherwani
1993	J	`jnl`	A provably good multilayer topological planar routing algorithm in IC layout designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jason Cong, Moazzem Hossain, Naveed A. Sherwani
1993	—	`book`	Algorithms for VLSI physical design automation. Naveed A. Sherwani
1993	J	`jnl`	Efficient Edge Domination Problems in Graphs. Inf. Process. Lett. Dana L. Grinstead, Peter J. Slater, Naveed A. Sherwani, Nancy D. Holmes
1993	C	`conf`	Efficient Over-the-cell Routing Algorithm for General Middle Terminal Model. ISCAS Siddharth Bhingarde, Anand Panyam, Naveed A. Sherwani
1993	J	`jnl`	Middle terminal cell models for efficient over-the-cell routing in high-performance circuits. IEEE Trans. Very Large Scale Integr. Syst. Siddharth Bhingarde, Anand Panyam, Naveed A. Sherwani
1993	Misc	`conf`	On Optimum Cell Models for Over-the-Cell Routing. VLSI Design Siddharth Bhingarde, Anand Panyam, Naveed A. Sherwani
1993	J	`jnl`	Programmable multichip modules. IEEE Micro Surendra Burman, Naveed A. Sherwani
1993	J	`jnl`	Utilization of vacant terminals for improved over-the-cell channel routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Nancy D. Holmes, Naveed A. Sherwani, Majid Sarrafzadeh
1992	J	`jnl`	A Parallel Algorithm for Single Row Routing Problems. J. Circuits Syst. Comput. Arnob Roy, Jitender S. Deogun, Naveed A. Sherwani
1992	A	`conf`	New channel segmentation model and associated routing algorithm for high performance FPGAs. ICCAD Surendra Burman, Chandar Kamalanathan, Naveed A. Sherwani
1992	A*	`conf`	Over-the-Cell Channel Routing for High Performance Circuits. DAC Sivakumar Natarajan, Naveed A. Sherwani, Nancy D. Holmes, Majid Sarrafzadeh
1992	A*	`conf`	Over-the-Cell Routers for New Cell Model. DAC Bo Wu, Naveed A. Sherwani, Nancy D. Holmes, Majid Sarrafzadeh
1992	A	`conf`	Zero skew clock routing in multiple-clock synchronous systems. ICCAD Wasim Khan, Moazzem Hossain, Naveed A. Sherwani
1991	A	`conf`	Algorithms for Three-Layer Over-The-Cell Channel Routing. ICCAD Nancy D. Holmes, Naveed A. Sherwani, Majid Sarrafzadeh
1991	C	`conf`	An Efficient Approximation Algorithm for Hypercube Scheduling. ICCI Alfred J. Boals, Ajay Gupta, Jahangir A. Hashmi, Naveed A. Sherwani
1991	C	`conf`	Compact Hypercubes: Properties and Recognition. ICCI Alfred J. Boals, Ajay K. Gupta, Jahangir A. Hashmi, Naveed A. Sherwani
1991	—	`ed.`	Computing in the 90's, The First Great Lakes Computer Science Conference, Kalamazzo, Michigan, USA, October 18-20, 1989, Proceedings Great Lakes Computer Science Conference Naveed A. Sherwani, Elise de Doncker, John A. Kapenga
1991	—	`conf`	Fully Normal Algorithms for Incomplete Hypercubes. IPPS Venkata K. Prabhala, Naveed A. Sherwani
1991	A*	`conf`	New Algorithm for Over-the-Cell Channel Routing Using Vacant Terminals. DAC Nancy D. Holmes, Naveed A. Sherwani, Majid Sarrafzadeh
1991	—	`conf`	On Optimal Embeddings into Incomplete Hypercubes. IPPS Ajay Gupta, Alfred J. Boals, Naveed A. Sherwani
1991	A	`conf`	On Topological Via Minimization and Routing. ICCAD Moazzem Hossain, Naveed A. Sherwani
1991	A	`conf`	Switchbox Steiner Tree Problem in Presence of Obstacles. ICCAD S. Miriyala, Jahangir A. Hashmi, Naveed A. Sherwani
1990	A*	`conf`	MISER: An Integrated Three Layer Gridless Channel Router and Compactor. DAC Roshan A. Gidwani, Naveed A. Sherwani
1989	A*	`conf`	A New Heuristic for Single Row Routing Problems. DAC Naveed A. Sherwani, Jitender S. Deogun