Naushad Alam

34 papers C 4Journal 13Unranked 17
YearRankTypeTitle / Venue / Authors
2024 — conf
A 0-24mA, 1.2V/1.8V Dual Mode Low Dropout Regulator Design for Efficient Power Management in Battery-Powered Systems.
VDAT
Munazir Reza, Naushad Alam, Syed Javed Gaggatur
2024 — conf
Memento 4.0: A Prototype Conversational Search System for LSC'24.
LSC@ICMR
Naushad Alam, Yvette Graham, Cathal Gurrin
2023 J jnl
Comparing Interactive Retrieval Approaches at the Lifelog Search Challenge 2021.
IEEE Access
Ly-Duyen Tran, Manh-Duy Nguyen, Duc-Tien Dang-Nguyen, Silvan Heller, Florian Spiess, Jakub Lokoc, Ladislav Peska, Thao-Nhu Nguyen, Omar Shahbaz Khan, Aaron Duane, Björn Þór Jónsson, Luca Rossetto, An-Zi Yen, Ahmed Alateeq, Naushad Alam, Minh-Triet Tran, Graham Healy, Klaus Schoeffmann, Cathal Gurrin
2023 — conf
DCU at the NTCIR17 Lifelog-5 Task.
NTCIR
Naushad Alam, Yvette Graham, Cathal Gurrin
2023 — conf
Memento 3.0: An Enhanced Lifelog Search Engine for LSC'23.
LSC@ICMR
Naushad Alam, Yvette Graham, Cathal Gurrin
2023 J jnl
Memento: a prototype search engine for LSC 2021.
Multim. Tools Appl.
Naushad Alam, Yvette Graham
2023 — conf
Overview of the NTCIR-17 Lifelog-5 Task.
NTCIR
Liting Zhou, Graham Healy, Cathal Gurrin, Ly-Duyen Tran, Naushad Alam, Hideo Joho, Longyue Wang, Tianbo Ji, Chenyang Lyu, Duc-Tien Dang-Nguyen
2022 C conf
An Exploration into the Benefits of the CLIP model for Lifelog Retrieval.
CBMI
Ly-Duyen Tran, Naushad Alam, Yvette Graham, Linh Khanh Vo, Nghiem Tuong Diep, Binh T. Nguyen, Liting Zhou, Cathal Gurrin
2022 — conf
DCU at the NTCIR16 Lifelog-4 Task.
NTCIR
Naushad Alam, Ahmed Alateeq, Yvette Graham, Mark Roantree, Cathal Gurrin
2022 — conf
Memento 2.0: An Improved Lifelog Search Engine for LSC'22.
LSC@ICMR
Naushad Alam, Yvette Graham, Cathal Gurrin
2021 — conf
Memento: A Prototype Lifelog Search Engine for LSC'21.
LSC@ICMR
Naushad Alam, Yvette Graham, Cathal Gurrin
2021 — conf
Radiation Hardened Area-Efficient 10T SRAM Cell for Space Applications.
VDAT
Sayeed Ahmad, Naushad Alam, Mohd. Hasan
2020 J jnl
Design approach to improve the performance of JAMFETs.
IET Circuits Devices Syst.
Mohd Adil Raushan, Naushad Alam, Mohd Jawaid Siddiqui
2020 J jnl
Design of CNTFET-Based CCII Using gm/ID Technique for Low-Voltage and Low-Power Applications.
J. Circuits Syst. Comput.
Mohd Yasir, Naushad Alam
2020 — conf
FPGA and ASIC Implementation and Comparison of Multipliers.
ISDCS
Salwa Yasmeen Neyaz, Itisha Saxena, Naushad Alam, Syed Atiqur Rahman
2020 J jnl
Suppression of ambipolarity in tunnel-FETs using gate oxide as parameter: analysis and investigation.
IET Circuits Devices Syst.
Syed Afzal Ahmad, Naushad Alam
2019 J jnl
Compact and Low Power 11T-2MTJ Non-Volatile Ternary Content Addressable Memory Cell with High Sense Margin.
J. Low Power Electron.
Ahmed Shaban, Sayeed Ahmad, Naushad Alam, Mohd. Hasan
2019 C conf
Pocket engineered electrostatically doped tunnel field effect transistor.
TENCON
Mohd Adil Raushan, Naushad Alam, Mohd Jawaid Siddiqui
2018 — conf
Compact and Reliable Low Power Non-Volatile TCAM Cell.
ISED
Ahmed Shaban, Sayeed Ahmad, Naushad Alam, Mohd. Hasan
2018 — conf
UTBB FD-SOI Circuit Design using Multifinger Transistors: A Circuit-Device Interaction Perspective.
PRIME
Arvind Kumar Sharma, Naushad Alam, Anand Bulusu
2017 J jnl
Low Leakage Single Bitline 9 T (SB9T) Static Random Access Memory.
Microelectron. J.
Sayeed Ahmad, Mohit Kumar Gupta, Naushad Alam, Mohd. Hasan
2016 J jnl
A variation aware timing model for a 2-input NAND gate and its use in sub-65 nm CMOS standard cell characterization.
Microelectron. J.
Baljit Kaur, Arvind Kumar Sharma, Naushad Alam, S. K. Manhas, Bulusu Anand
2016 J jnl
Single-Ended Schmitt-Trigger-Based Robust Low-Power SRAM Cell.
IEEE Trans. Very Large Scale Integr. Syst.
Sayeed Ahmad, Mohit Kumar Gupta, Naushad Alam, Mohd. Hasan
2015 — conf
Pre-layout estimation of performance and design of basic analog circuits in stress enabled technologies.
VDAT
Arvind Kumar Sharma, Neeraj Mishra, Naushad Alam, Sudeb Dasgupta, Anand Bulusu
2014 J jnl
An Analytical Delay Model for Mechanical Stress Induced Systematic Variability Analysis in Nanoscale Circuit Design.
IEEE Trans. Circuits Syst. I Regul. Pap.
Naushad Alam, Bulusu Anand, Sudeb Dasgupta
2014 — conf
An analytical delay model for CMOS Inverter-Transmission Gate structure.
VDAT
Mohammad Shueb Romi, Naushad Alam, Mohd Yusuf Yasin
2014 J jnl
Efficient ECSM Characterization Considering Voltage, Temperature, and Mechanical Stress Variability.
IEEE Trans. Circuits Syst. I Regul. Pap.
Baljit Kaur, Naushad Alam, S. K. Manhas, Bulusu Anand
2013 J jnl
The impact of process-induced mechanical stress in narrow width devices and variable-taper CMOS buffer design.
Microelectron. Reliab.
Naushad Alam, Bulusu Anand, Sudeb Dasgupta
2013 J jnl
The impact of process-induced mechanical stress on CMOS buffer design using multi-fingered devices.
Microelectron. Reliab.
Naushad Alam, Bulusu Anand, Sudeb Dasgupta
2012 — conf
Impact of Dummy Poly on the Process-Induced Mechanical Stress Enhanced Circuit Performance.
VDAT
Naushad Alam, Bulusu Anand, Sudeb Dasgupta
2012 — conf
Process induced mechanical stress aware poly-pitch optimization for enhanced circuit performance.
ISQED
Naushad Alam, Bulusu Anand, Sudeb Dasgupta
2012 — conf
The Impact of Process-Induced Mechanical Stress in Narrow Width Devices and Circuit Design Issues.
ISED
Naushad Alam, Bulusu Anand, Sudeb Dasgupta
2009 C conf
Carbon Nanotube Interconnects for Low-power High-speed Applications.
ISCAS
Naushad Alam, Abdul Kadir Kureshi, Mohd. Hasan, Tughrul Arslan
2009 C conf
Subthreshold Deep Submicron Performance Investigation of CMOS and DTCMOS Biasing Schemes for Reconfigurable Computing.
ISCAS
Abdul Kadir Kureshi, Naushad Alam, Mohd. Hasan, Tughrul Arslan