Natesan Venkateswaran

13 papers A* 4A 1C 1Misc 2Journal 2Unranked 3

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	Radial basis function networks-based resource-aware offloading video analytics in mobile edge computing. Wirel. Networks Jothi Prabha Appadurai, Prabaharan Sengodan, Natesan Venkateswaran, S. Abijah Roseline, B. Rama
2016	A*	`conf`	A distributed timing analysis framework for large designs. DAC Tsung-Wei Huang, Martin D. F. Wong, Debjit Sinha, Kerim Kalafala, Natesan Venkateswaran
2016	Misc	`conf`	Sharing and Re-use of Statistical Timing Macro-Models across Multiple Voltage Domains. VLSID Debjit Sinha, Vladimir Zolotov, Eric Fluhr, Michael H. Wood, Jeffrey Ritzinger, Natesan Venkateswaran, Stephen Shuma
2012	A*	`conf`	Reversible statistical DAC Debjit Sinha, Chandu Visweswariah, Natesan Venkateswaran, Jinjun Xiong, Vladimir Zolotov
2012	A*	`conf`	Timing analysis with nonseparable statistical and deterministic variations. DAC Vladimir Zolotov, Debjit Sinha, Jeffrey G. Hemmett, Eric A. Foreman, Chandu Visweswariah, Jinjun Xiong, Jeremy Leitzen, Natesan Venkateswaran
2006	A*	`conf`	Criticality computation in parameterized statistical timing. DAC Jinjun Xiong, Vladimir Zolotov, Natesan Venkateswaran, Chandu Visweswariah
2006	J	`jnl`	First-Order Incremental Block-Based Statistical Timing Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chandramouli Visweswariah, K. Ravindran, Kerim Kalafala, Steven G. Walker, S. Narayan, Daniel K. Beece, Jeff Piaget, Natesan Venkateswaran, Jeffrey G. Hemmett
2005	A	`conf`	Gate sizing using incremental parameterized statistical timing analysis. ICCAD Matthew R. Guthaus, Natesan Venkateswaran, Chandu Visweswariah, Vladimir Zolotov
2005	—	`conf`	Optimization objectives and models of variation for statistical gate sizing. ACM Great Lakes Symposium on VLSI Matthew R. Guthaus, Natesan Venkateswaran, Vladimir Zolotov, Dennis Sylvester, Richard B. Brown
1999	—	`conf`	Congestion Mitigation During Placement. Great Lakes Symposium on VLSI Kanad Chakraborty, Natesan Venkateswaran
1998	C	`conf`	Clock-skew constrained placement for row based designs. ICCD Natesan Venkateswaran, Dinesh Bhatia
1997	—	`conf`	A constructive method for data path area estimation during high-level VLSI synthesis. ASP-DAC Natesan Venkateswaran, Anurag Gupta, Srinivas Katkoori, Dinesh Bhatia, Ranga Vemuri
1996	Misc	`conf`	Clock-Skew Constrained Cell Placement. VLSI Design Natesan Venkateswaran, Dinesh Bhatia