Naresh Sehgal

12 papers A* 1A 2Misc 2Journal 2Unranked 5
YearRankTypeTitle / Venue / Authors
2003 — conf
A novel ultra-fast heuristic for VLSI CAD steiner trees.
ACM Great Lakes Symposium on VLSI
Bharat Krishna, C. Y. Roger Chen, Naresh Sehgal
2003 — conf
Detailed Placement with Net Length Constraints.
IWSOC
Bill Halpin, Naresh Sehgal, C. Y. Roger Chen
2001 A* conf
Timing Driven Placement using Physical Net Constraints.
DAC
Bill Halpin, C. Y. Roger Chen, Naresh Sehgal
2000 — conf
A novel technique for sea of gates global routing.
ACM Great Lakes Symposium on VLSI
Bharat Krishna, C. Y. Roger Chen, Naresh Sehgal
2000 — conf
A sensitivity based placer for standard cells.
ACM Great Lakes Symposium on VLSI
Bill Halpin, C. Y. Roger Chen, Naresh Sehgal
1999 J jnl
Extraction of functional regularity in datapath circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Amit Chowdhary, Sudhakar Kale, Phani K. Saripella, Naresh Sehgal, Rajesh K. Gupta
1999 Misc conf
GeneSys: A Leaf-Cell Layout Synthesis System for GHz VLSI Designs.
VLSI Design
Bülent Basaran, Kiran Ganesh, Raymond Y. K. Lau, Artour Levin, Miles McCoo, Srinivasan Rangarajan, Naresh Sehgal
1998 A conf
A general approach for regularity extraction in datapath circuits.
ICCAD
Amit Chowdhary, Sudhakar Kale, Phani K. Saripella, Naresh Sehgal, Rajesh K. Gupta
1998 Misc conf
Technique for Planning of Terminal Locations of Leaf Cells in Cell-Based Design with Routing Considerations.
VLSI Design
Bharat Krishna, C. Y. Roger Chen, Naresh Sehgal
1995 J jnl
Power conscious CAD tools and methodologies: a perspective.
Proc. IEEE
Deo Singh, Jan M. Rabaey, Massoud Pedram, Francky Catthoor, Suresh Rajgopal, Naresh Sehgal, Thomas J. Mozdzen
1994 — conf
A gridless multi-layer area router.
Great Lakes Symposium on VLSI
Naresh Sehgal, C. Y. Roger Chen, John M. Acken
1994 A conf
An object-oriented cell library manager.
ICCAD
Naresh Sehgal, C. Y. Roger Chen, John M. Acken