Naresh R. Shanbhag

258 papers A* 11A 31B 5C 19Misc 26Journal 112Unranked 52

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	AI+HW 2035: Shaping the Next Decade. CoRR Deming Chen, Jason Cong, Azalia Mirhoseini, Christos Kozyrakis, Subhasish Mitra, Jinjun Xiong, Cliff Young, Anima Anandkumar, Michael L. Littman, Aron Kirschen, Sophia Shao, Serge Leef, Naresh R. Shanbhag, Dejan S. Milojicic, Michael Schulte, Gert Cauwenberghs, Jerry M. Chow, Tri Dao, Kailash Gopalakrishnan, Richard Ho, Hoshik Kim, Kunle Olukotun, David Z. Pan, Mark Ren, Dan Roth, Aarti Singh, Yizhou Sun, Yusu Wang, Yann LeCun, Ruchir Puri
2026	J	`jnl`	Characterizing the Intrinsic Bank-Level Accuracy Versus Energy Trade-Off of SRAM-Based Analog In-Memory Computing Architectures in 28 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Shuo Li, Chihun Song, Hyungyo Kim, Nam Sung Kim, Naresh R. Shanbhag
2026	J	`jnl`	Energy-Accuracy Trade-Offs in Massive MIMO Signal Detection Using SRAM-Based In-Memory Computing. IEEE Trans. Circuits Syst. I Regul. Pap. Mihir Kavishwar, Naresh R. Shanbhag
2025	J	`jnl`	Compute SNDR-Boosted 22-nm MRAM-Based In-Memory Computing Macro Using Statistical Error Compensation. IEEE J. Solid State Circuits Saion K. Roy, Han-Mo Ou, Mostafa Gamal Ahmed, Peter Deaville, Bonan Zhang, Naveen Verma, Pavan Kumar Hanumolu, Naresh R. Shanbhag
2024	J	`jnl`	Enhancing the Accuracy of 6T SRAM-Based In-Memory Architecture via Maximum Likelihood Detection. IEEE Trans. Signal Process. Hyungyo Kim, Naresh R. Shanbhag
2024	A	`conf`	On the Security Vulnerabilities of MRAM-based In-Memory Computing Architectures against Model Extraction Attacks. ICCAD Saion K. Roy, Naresh R. Shanbhag
2023	Misc	`conf`	Boosting the Accuracy of SRAM-Based in-Memory Architectures Via Maximum Likelihood-Based Error Compensation Method. ICASSP Hyungyo Kim, Naresh R. Shanbhag
2023	—	`conf`	Compute SNR-boosted 22 nm MRAM-based In-memory Computing Macro using Statistical Error Compensation. ESSCIRC Saion K. Roy, Han-Mo Ou, Mostafa Gamal Ahmed, Peter Deaville, Bonan Zhang, Naveen Verma, Pavan Kumar Hanumolu, Naresh R. Shanbhag
2023	Misc	`conf`	Enhancing the Accuracy of Resistive In-Memory Architectures using Adaptive Signal Processing. ICASSP Han-Mo Ou, Naresh R. Shanbhag
2023	A*	`conf`	On the Robustness of Randomized Ensembles to Adversarial Perturbations. ICML Hassan Dbouk, Naresh R. Shanbhag
2023	J	`jnl`	On the Robustness of Randomized Ensembles to Adversarial Perturbations. CoRR Hassan Dbouk, Naresh R. Shanbhag
2023	A	`conf`	PRIVE: Efficient RRAM Programming with Chip Verification for RRAM-based In-Memory Computing Acceleration. DATE Wangxin He, Jian Meng, Sujan Kumar Gonugondla, Shimeng Yu, Naresh R. Shanbhag, Jae-sun Seo
2022	A*	`conf`	Adversarial Vulnerability of Randomized Ensembles. ICML Hassan Dbouk, Naresh R. Shanbhag
2022	J	`jnl`	Adversarial Vulnerability of Randomized Ensembles. CoRR Hassan Dbouk, Naresh R. Shanbhag
2022	—	`conf`	Comprehending In-memory Computing Trends via Proper Benchmarking. CICC Naresh R. Shanbhag, Saion K. Roy
2022	J	`jnl`	Coordinated Science Laboratory 70th Anniversary Symposium: The Future of Computing. CoRR Klara Nahrstedt, Naresh R. Shanbhag, Vikram S. Adve, Nancy M. Amato, Romit Roy Choudhury, Carl A. Gunter, Nam Sung Kim, Olgica Milenkovic, Sayan Mitra, Lav R. Varshney, Yurii Vlasov, Sarita V. Adve, Rashid Bashir, Andreas Cangellaris, James DiCarlo, Katie Driggs-Campbell, Nick Feamster, Mattia Gazzola, Karrie Karahalios, Sanmi Koyejo, Paul G. Kwiat, Bo Li, Negar Mehr, Ravish Mehra, Andrew Miller, Daniela Rus, Alexander G. Schwing, Anshumali Shrivastava
2022	J	`jnl`	Fundamental Limits on Energy-Delay-Accuracy of In-Memory Architectures in Inference Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sujan K. Gonugondla, Charbel Sakr, Hassan Dbouk, Naresh R. Shanbhag
2022	C	`conf`	Fundamental Limits on the Computational Accuracy of Resistive Crossbar-based In-memory Architectures. ISCAS Saion K. Roy, Ameya Patil, Naresh R. Shanbhag
2022	Misc	`conf`	IMPQ: Reduced Complexity Neural Networks Via Granular Precision Assignment. ICASSP Sujan Kumar Gonugondla, Naresh R. Shanbhag
2021	J	`jnl`	A 0.44-μJ/dec, 39.9-μs/dec, Recurrent Attention In-Memory Processor for Keyword Spotting. IEEE J. Solid State Circuits Hassan Dbouk, Sujan K. Gonugondla, Charbel Sakr, Naresh R. Shanbhag
2021	A*	`conf`	Generalized Depthwise-Separable Convolutions for Adversarially Robust and Efficient Neural Networks. NeurIPS Hassan Dbouk, Naresh R. Shanbhag
2021	J	`jnl`	Generalized Depthwise-Separable Convolutions for Adversarially Robust and Efficient Neural Networks. CoRR Hassan Dbouk, Naresh R. Shanbhag
2021	A	`conf`	Optimizing Selective Protection for CNN Resilience. ISSRE Abdulrahman Mahmoud, Siva Kumar Sastry Hari, Christopher W. Fletcher, Sarita V. Adve, Charbel Sakr, Naresh R. Shanbhag, Pavlo Molchanov, Michael B. Sullivan, Timothy Tsai, Stephen W. Keckler
2021	J	`jnl`	Robustifying 𝓁 CoRR Ameya D. Patil, Michael Tuttle, Alexander G. Schwing, Naresh R. Shanbhag
2021	—	`conf`	SE1: What Technologies Will Shape the Future of Computing? ISSCC Hugh Mair, Shinichiro Shiratake, Eric Karl, Thomas Burd, Jonathan Chang, Debbie Marr, Samuel Naffziger, Henk Corporaal, Ken Takeuchi, Naresh R. Shanbhag
2021	J	`jnl`	Signal Processing Methods to Enhance the Energy Efficiency of In-Memory Computing Architectures. IEEE Trans. Signal Process. Charbel Sakr, Naresh R. Shanbhag
2020	—	`conf`	DBQ: A Differentiable Branch Quantizer for Lightweight Deep Neural Networks. ECCV (27) Hassan Dbouk, Hetul Sanghvi, Mahesh Mehendale, Naresh R. Shanbhag
2020	J	`jnl`	DBQ: A Differentiable Branch Quantizer for Lightweight Deep Neural Networks. CoRR Hassan Dbouk, Hetul Sanghvi, Mahesh Mehendale, Naresh R. Shanbhag
2020	J	`jnl`	Deep In-Memory Architectures for Machine Learning-Accuracy Versus Efficiency Trade-Offs. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. Mingu Kang, Yongjune Kim, Ameya D. Patil, Naresh R. Shanbhag
2020	J	`jnl`	Deep In-Memory Architectures in SRAM: An Analog Approach to Approximate Computing. Proc. IEEE Mingu Kang, Sujan K. Gonugondla, Naresh R. Shanbhag
2020	J	`jnl`	Fundamental Limits on Energy-Delay-Accuracy of In-memory Architectures in Inference Applications. CoRR Sujan Kumar Gonugondla, Charbel Sakr, Hassan Dbouk, Naresh R. Shanbhag
2020	A	`conf`	Fundamental Limits on the Precision of In-memory Architectures. ICCAD Sujan K. Gonugondla, Charbel Sakr, Hassan Dbouk, Naresh R. Shanbhag
2020	J	`jnl`	HarDNN: Feature Map Vulnerability Evaluation in CNNs. CoRR Abdulrahman Mahmoud, Siva Kumar Sastry Hari, Christopher W. Fletcher, Sarita V. Adve, Charbel Sakr, Naresh R. Shanbhag, Pavlo Molchanov, Michael B. Sullivan, Timothy Tsai, Stephen W. Keckler
2020	—	`conf`	KeyRAM: A 0.34 uJ/decision 18 k decisions/s Recurrent Attention In-memory Processor for Keyword Spotting. CICC Hassan Dbouk, Sujan K. Gonugondla, Charbel Sakr, Naresh R. Shanbhag
2020	Misc	`conf`	Low-Complexity Fixed-Point Convolutional Neural Networks For Automatic Target Recognition. ICASSP Hassan Dbouk, Hanfei Geng, Craig M. Vineyard, Naresh R. Shanbhag
2020	J	`jnl`	Nanotechnology-inspired Information Processing Systems of the Future. CoRR Randy Bryant, Mark D. Hill, Tom Kazior, Daniel Lee, Jie Liu, Klara Nahrstedt, Vijay Narayanan, Jan M. Rabaey, Hava T. Siegelmann, Naresh R. Shanbhag, Naveen Verma, H.-S. Philip Wong
2020	A	`conf`	SWIPE: Enhancing Robustness of ReRAM Crossbars for In-memory Computing. ICCAD Sujan K. Gonugondla, Ameya D. Patil, Naresh R. Shanbhag
2019	—	`conf`	Accumulation Bit-Width Scaling For Ultra-Low Precision Training Of Deep Networks. ICLR (Poster) Charbel Sakr, Naigang Wang, Chia-Yu Chen, Jungwook Choi, Ankur Agrawal, Naresh R. Shanbhag, Kailash Gopalakrishnan
2019	J	`jnl`	Accumulation Bit-Width Scaling For Ultra-Low Precision Training Of Deep Networks. CoRR Charbel Sakr, Naigang Wang, Chia-Yu Chen, Jungwook Choi, Ankur Agrawal, Naresh R. Shanbhag, Kailash Gopalakrishnan
2019	C	`conf`	An Energy-Efficient Classifier via Boosted Spin Channel Networks. ISCAS Ameya D. Patil, Sasikanth Manipatruni, Dmitri E. Nikonov, Ian A. Young, Naresh R. Shanbhag
2019	J	`jnl`	An Energy-Efficient Programmable Mixed-Signal Accelerator for Machine Learning Algorithms. IEEE Micro Mingu Kang, Prakalp Srivastava, Vikram S. Adve, Nam Sung Kim, Naresh R. Shanbhag
2019	C	`conf`	An MRAM-Based Deep In-Memory Architecture for Deep Neural Networks. ISCAS Ameya D. Patil, Haocheng Hua, Sujan K. Gonugondla, Mingu Kang, Naresh R. Shanbhag
2019	J	`jnl`	Efficient Local Secret Sharing for Distributed Blockchain Systems. IEEE Commun. Lett. Yongjune Kim, Ravi Kiran Raman, Young-Sik Kim, Lav R. Varshney, Naresh R. Shanbhag
2019	J	`jnl`	Minimum Precision Requirements of General Margin Hyperplane Classifiers. IEEE J. Emerg. Sel. Topics Circuits Syst. Charbel Sakr, Yongjune Kim, Naresh R. Shanbhag
2019	—	`conf`	Per-Tensor Fixed-Point Quantization of the Back-Propagation Algorithm. ICLR (Poster) Charbel Sakr, Naresh R. Shanbhag
2019	J	`jnl`	Shannon-Inspired Statistical Computing for the Nanoscale Era. Proc. IEEE Naresh R. Shanbhag, Naveen Verma, Yongjune Kim, Ameya D. Patil, Lav R. Varshney
2018	J	`jnl`	A 19.4-nJ/Decision, 364-K Decisions/s, In-Memory Random Forest Multi-Class Inference Accelerator. IEEE J. Solid State Circuits Mingu Kang, Sujan K. Gonugondla, Sungmin Lim, Naresh R. Shanbhag
2018	—	`conf`	A 42pJ/decision 3.12TOPS/W robust in-memory machine learning classifier with on-chip training. ISSCC Sujan Kumar Gonugondla, Mingu Kang, Naresh R. Shanbhag
2018	J	`jnl`	A Multi-Functional In-Memory Inference Processor Using a Standard 6T SRAM Array. IEEE J. Solid State Circuits Mingu Kang, Sujan K. Gonugondla, Ameya Patil, Naresh R. Shanbhag
2018	J	`jnl`	A Rank Decomposed Statistical Error Compensation Technique for Robust Convolutional Neural Networks in the Near Threshold Voltage Regime. J. Signal Process. Syst. Yingyan Lin, Sai Zhang, Naresh R. Shanbhag
2018	J	`jnl`	A Variation-Tolerant In-Memory Machine Learning Classifier via On-Chip Training. IEEE J. Solid State Circuits Sujan K. Gonugondla, Mingu Kang, Naresh R. Shanbhag
2018	Misc	`conf`	An Analytical Method to Determine Minimum Per-Layer Precision of Deep Neural Networks. ICASSP Charbel Sakr, Naresh R. Shanbhag
2018	J	`jnl`	An In-Memory VLSI Architecture for Convolutional Neural Networks. IEEE J. Emerg. Sel. Topics Circuits Syst. Mingu Kang, Sungmin Lim, Sujan K. Gonugondla, Naresh R. Shanbhag
2018	C	`conf`	Energy-Efficient Deep In-memory Architecture for NAND Flash Memories. ISCAS Sujan K. Gonugondla, Mingu Kang, Yongjune Kim, Mark Helm, Sean Eilert, Naresh R. Shanbhag
2018	J	`jnl`	Generalized Water-Filling for Source-Aware Energy-Efficient SRAMs. IEEE Trans. Commun. Yongjune Kim, Mingu Kang, Lav R. Varshney, Naresh R. Shanbhag
2018	—	`conf`	Minimum Precision Requirements for Deep Learning with Biomedical Datasets. BioCAS Charbel Sakr, Naresh R. Shanbhag
2018	A*	`conf`	PROMISE: An End-to-End Design of a Programmable Mixed-Signal Accelerator for Machine-Learning Algorithms. ISCA Prakalp Srivastava, Mingu Kang, Sujan K. Gonugondla, Sungmin Lim, Jungwook Choi, Vikram S. Adve, Nam Sung Kim, Naresh R. Shanbhag
2018	J	`jnl`	Per-Tensor Fixed-Point Quantization of the Back-Propagation Algorithm. CoRR Charbel Sakr, Naresh R. Shanbhag
2018	B	`conf`	SRAM Bit-line Swings Optimization using Generalized Waterfilling. ISIT Yongjune Kim, Mingu Kang, Lav R. Varshney, Naresh R. Shanbhag
2018	Misc	`conf`	True Gradient-Based Training of Deep Binary Activated Neural Networks Via Continuous Binarization. ICASSP Charbel Sakr, Jungwook Choi, Zhuo Wang, Kailash Gopalakrishnan, Naresh R. Shanbhag
2017	—	`conf`	A 19.4 nJ/decision 364K decisions/s in-memory random forest classifier in 6T SRAM array. ESSCIRC Mingu Kang, Sujan K. Gonugondla, Naresh R. Shanbhag
2017	A*	`conf`	A Systems Approach to Computing in Beyond CMOS Fabrics: Invited. DAC Ameya Patil, Naresh R. Shanbhag, Lav R. Varshney, Eric Pop, H.-S. Philip Wong, Subhasish Mitra, Jan M. Rabaey, Jeffrey A. Weldon, Larry T. Pileggi, Sasikanth Manipatruni, Dmitri E. Nikonov, Ian A. Young
2017	A*	`conf`	Analytical Guarantees on Numerical Precision of Deep Neural Networks. ICML Charbel Sakr, Yongjune Kim, Naresh R. Shanbhag
2017	J	`jnl`	Generalized Water-filling for Source-Aware Energy-Efficient SRAMs. CoRR Yongjune Kim, Mingu Kang, Lav R. Varshney, Naresh R. Shanbhag
2017	Misc	`conf`	Minimum precision requirements for the SVM-SGD learning algorithm. ICASSP Charbel Sakr, Ameya Patil, Sai Zhang, Yongjune Kim, Naresh R. Shanbhag
2017	C	`conf`	PredictiveNet: An energy-efficient convolutional neural network via zero prediction. ISCAS Yingyan Lin, Charbel Sakr, Yongjune Kim, Naresh R. Shanbhag
2017	J	`jnl`	Shannon-inspired Statistical Computing to Enable Spintronics. CoRR Ameya D. Patil, Sasikanth Manipatruni, Dmitri E. Nikonov, Ian A. Young, Naresh R. Shanbhag
2017	J	`jnl`	Slicer Architectures for Analog-to-Information Conversion in Channel Equalizers. IEEE Trans. Commun. Aseem Wadhwa, Upamanyu Madhow, Naresh R. Shanbhag
2016	J	`jnl`	A 481pJ/decision 3.4M decision/s Multifunctional Deep In-memory Inference Processor using Standard 6T SRAM Array. CoRR Mingu Kang, Sujan K. Gonugondla, Ameya Patil, Naresh R. Shanbhag
2016	J	`jnl`	A Study of BER-Optimal ADC-Based Receiver for Serial Links. IEEE Trans. Circuits Syst. I Regul. Pap. Yingyan Lin, Min-Sun Keel, Adam C. Faust, Aolin Xu, Naresh R. Shanbhag, Elyse Rosenbaum, Andrew C. Singer
2016	Misc	`conf`	Analysis of error resiliency of belief propagation in computer vision. ICASSP Jungwook Choi, Ameya D. Patil, Rob A. Rutenbar, Naresh R. Shanbhag
2016	J	`jnl`	Correction to "An Energy-Efficient ECG Processor in 45-nm CMOS Using Statistical Error Compensation". IEEE J. Solid State Circuits Rami A. Abdallah, Naresh R. Shanbhag
2016	J	`jnl`	Embedded Algorithmic Noise-Tolerance for Signal Processing and Machine Learning Systems via Data Path Decomposition. IEEE Trans. Signal Process. Sai Zhang, Naresh R. Shanbhag
2016	J	`jnl`	Energy-efficient Machine Learning in Silicon: A Communications-inspired Approach. CoRR Naresh R. Shanbhag
2016	J	`jnl`	Error Resilient and Energy Efficient MRF Message-Passing-Based Stereo Matching. IEEE Trans. Very Large Scale Integr. Syst. Eric P. Kim, Jungwook Choi, Naresh R. Shanbhag, Rob A. Rutenbar
2016	J	`jnl`	Error-Resilient Machine Learning in Near Threshold Voltage via Classifier Ensemble. CoRR Sai Zhang, Naresh R. Shanbhag
2016	J	`jnl`	In-Memory Computing Architectures for Sparse Distributed Memory. IEEE Trans. Biomed. Circuits Syst. Mingu Kang, Naresh R. Shanbhag
2016	Misc	`conf`	Perfect error compensation via algorithmic error cancellation. ICASSP Sujan K. Gonugondla, Byonghyo Shim, Naresh R. Shanbhag
2016	A	`conf`	Probabilistic Error Models for machine learning kernels implemented on stochastic nanoscale fabrics. DATE Sai Zhang, Naresh R. Shanbhag
2016	J	`jnl`	Reducing the Energy Cost of Inference via In-sensor Information Processing. CoRR Sai Zhang, Mingu Kang, Charbel Sakr, Naresh R. Shanbhag
2016	J	`jnl`	Understanding the Energy and Precision Requirements for Online Learning. CoRR Charbel Sakr, Ameya Patil, Sai Zhang, Naresh R. Shanbhag
2016	—	`conf`	Variation-Tolerant Architectures for Convolutional Neural Networks in the Near Threshold Voltage Regime. SiPS Yingyan Lin, Sai Zhang, Naresh R. Shanbhag
2015	J	`jnl`	A 3.6-mW 50-MHz PN Code Acquisition Filter via Statistical Error Compensation in 180-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. Eric P. Kim, Daniel J. Baker, Sriram Narayanan, Naresh R. Shanbhag, Douglas L. Jones
2015	Misc	`conf`	An energy-efficient memory-based high-throughput VLSI architecture for convolutional networks. ICASSP Mingu Kang, Sujan K. Gonugondla, Min-Sun Keel, Naresh R. Shanbhag
2015	C	`conf`	Energy-efficient and high throughput sparse distributed memory architecture. ISCAS Mingu Kang, Eric P. Kim, Min-Sun Keel, Naresh R. Shanbhag
2015	A	`conf`	Reduced Overhead Error Compensation for Energy Efficient Machine Learning Kernels. ICCAD Sai Zhang, Naresh R. Shanbhag
2015	A	`conf`	Statistical information processing: Computing for the nanoscale era. ISLPED Naresh R. Shanbhag
2014	J	`jnl`	A 0.79 pJ/K-Gate, 83% Efficient Unified Core and Voltage Regulator Architecture for Sub/Near-Threshold Operation in 130 nm CMOS. IEEE J. Solid State Circuits Sai Zhang, Jane S. Tu, Naresh R. Shanbhag, Philip T. Krein
2014	Misc	`conf`	A robust message passing based stereo matching kernel via system-level error resiliency. ICASSP Eric P. Kim, Jungwook Choi, Naresh R. Shanbhag, Rob A. Rutenbar
2014	Misc	`conf`	An energy-efficient VLSI architecture for pattern recognition via deep embedding of computation in SRAM. ICASSP Mingu Kong, Min-Sun Keel, Naresh R. Shanbhag, Sean Eilert, Ken Curewitz
2014	—	`conf`	Embedded error compensation for energy efficient DSP systems. GlobalSIP Sai Zhang, Naresh R. Shanbhag
2014	—	`conf`	Energy-efficient accelerator architecture for stereo image matching using approximate computing and statistical error compensation. GlobalSIP Eric P. Kim, Naresh R. Shanbhag
2014	A	`conf`	Energy-efficient dot product computation using a switched analog circuit architecture. ISLPED Ihab Nahlus, Eric P. Kim, Naresh R. Shanbhag, David T. Blaauw
2014	J	`jnl`	Reducing Energy at the Minimum Energy Operating Point Via Statistical Error Compensation. IEEE Trans. Very Large Scale Integr. Syst. Rami A. Abdallah, Naresh R. Shanbhag
2014	—	`conf`	Space-time slicer architectures for analog-to-information conversion in channel equalizers. ICC Aseem Wadhwa, Upamanyu Madhow, Naresh R. Shanbhag
2014	J	`jnl`	System-Level Optimization of Switched-Capacitor VRM and Core for Sub/Near-V IEEE Trans. Circuits Syst. II Express Briefs Sai Zhang, Naresh R. Shanbhag, Philip T. Krein
2013	J	`jnl`	An Energy-Efficient ECG Processor in 45-nm CMOS Using Statistical Error Compensation. IEEE J. Solid State Circuits Rami A. Abdallah, Naresh R. Shanbhag
2013	—	`conf`	Error resilient MRF message passing architecture for stereo matching. SiPS Jungwook Choi, Eric P. Kim, Rob A. Rutenbar, Naresh R. Shanbhag
2013	—	`conf`	Error-resilient systems via statistical signal processing. SiPS Rami A. Abdallah, Naresh R. Shanbhag
2013	J	`jnl`	Robust and Energy Efficient Multimedia Systems via Likelihood Processing. IEEE Trans. Multim. Rami A. Abdallah, Naresh R. Shanbhag
2013	—	`ch.`	Signal Processing for High-Speed Links. Handbook of Signal Processing Systems Naresh R. Shanbhag, Andrew C. Singer, Hyeon-Min Bae
2013	Misc	`conf`	Statistical analysis of algorithmic noise tolerance. ICASSP Eric P. Kim, Naresh R. Shanbhag
2012	—	`conf`	A 14.5 fJ/cycle/k-gate, 0.33 V ECG processor in 45nm CMOS using statistical error compensation. CICC Rami A. Abdallah, Naresh R. Shanbhag
2012	Misc	`conf`	A fully automated technique for constructing FSM abstractions of non-ideal latches in communication systems. ICASSP Aadithya V. Karthik, Yingyan Lin, Chenjie Gu, Aolin Xu, Jaijeet S. Roychowdhury, Naresh R. Shanbhag
2012	—	`conf`	A sphere decoding approach for the vector Viterbi algorithm. ACSCC Peter Kairouz, Aolin Xu, Naresh R. Shanbhag, Andrew C. Singer
2012	J	`jnl`	BER-Optimal Analog-to-Digital Converters for Communication Links. IEEE Trans. Signal Process. Rajan Narasimha, Minwei Lu, Naresh R. Shanbhag, Andrew C. Singer
2012	—	`conf`	Energy-Efficient LDPC Decoders Based on Error-Resiliency. SiPS Eric P. Kim, Naresh R. Shanbhag
2012	—	`conf`	FEC-based 4 Gb/s backplane transceiver in 90nm CMOS. CICC Adam C. Faust, Rajan Narasimha, Karan S. Bhatia, Ankit Srivastava, Chhay Kong, Hyeon-Min Bae, Elyse Rosenbaum, Naresh R. Shanbhag
2012	A	`ed.`	International Symposium on Low Power Electronics and Design, ISLPED'12, Redondo Beach, CA, USA - July 30 - August 01, 2012 ISLPED Naresh R. Shanbhag, Massimo Poncino, Pai H. Chou, Ajith Amerasekera
2012	J	`jnl`	Soft N-Modular Redundancy. IEEE Trans. Computers Eric P. Kim, Naresh R. Shanbhag
2012	Misc	`conf`	System-driven metrics for the design and adaptation of analog to digital converters. ICASSP Rajan Narasimha, Georg Zeitler, Naresh R. Shanbhag, Andrew C. Singer, Gerhard Kramer
2011	—	`conf`	An energy-efficient multiple-input multiple-output (MIMO) detector architecture. SiPS Eric P. Kim, Naresh R. Shanbhag
2011	Misc	`conf`	Least squares approximation and polyphase decomposition for pipelining recursive filters. ICASSP Aditya Gupta, Andrew C. Singer, Naresh R. Shanbhag
2011	—	`conf`	Low power and error resilient PN code acquisition filter via statistical error compensation. CICC Eric P. Kim, Daniel J. Baker, Sriram Narayanan, Douglas L. Jones, Naresh R. Shanbhag
2011	A	`conf`	System energy minimization via joint optimization of the DC-DC converter and the core. ISLPED Rami A. Abdallah, Pradeep S. Shenoy, Naresh R. Shanbhag, Philip T. Krein
2011	A	`conf`	System-assisted analog mixed-signal design. DATE Naresh R. Shanbhag, Andrew C. Singer
2011	A	`conf`	Timing error statistics for energy-efficient robust DSP systems. DATE Rami A. Abdallah, Yu-Hung Lee, Naresh R. Shanbhag
2011	J	`jnl`	VLSI Architectures for Soft-Decision Decoding of Reed-Solomon Codes. IEEE Trans. Inf. Theory Arshad Ahmed, Ralf Koetter, Naresh R. Shanbhag
2010	C	`conf`	BER-optimal analog-to-digital converters for communication links. ISCAS Minwei Lu, Naresh R. Shanbhag, Andrew C. Singer
2010	J	`jnl`	Computation as estimation: a general framework for robustness and energy efficiency in SoCs. IEEE Trans. Signal Process. Sriram Narayanan, Girish Varatkar, Douglas L. Jones, Naresh R. Shanbhag
2010	J	`jnl`	Design of Energy-Efficient High-Speed Links via Forward Error Correction. IEEE Trans. Circuits Syst. II Express Briefs Rajan Narasimha, Naresh R. Shanbhag
2010	—	`conf`	Energy-efficient high-speed interfaces. ISSCC Naresh R. Shanbhag, Koichi Yamaguchi, Robert Payne
2010	J	`jnl`	Minimum-Energy Operation Via Error Resiliency. IEEE Embed. Syst. Lett. Rami A. Abdallah, Naresh R. Shanbhag
2010	A	`ed.`	Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010 ISLPED Vojin G. Oklobdzija, Barry Pangle, Naehyuck Chang, Naresh R. Shanbhag, Chris H. Kim
2010	C	`conf`	Robust and energy-efficient DSP systems via output probability processing. ICCD Rami A. Abdallah, Naresh R. Shanbhag
2010	—	`ch.`	Signal Processing for High-Speed Links. Handbook of Signal Processing Systems Naresh R. Shanbhag, Andrew C. Singer, Hyeon-Min Bae
2010	Misc	`conf`	Soft NMR: Analysis & application to DSP systems. ICASSP Eric P. Kim, Naresh R. Shanbhag
2010	J	`jnl`	Stochastic Networked Computation. IEEE Trans. Very Large Scale Integr. Syst. Girish Varatkar, Shrikanth S. Narayanan, Naresh R. Shanbhag, Douglas L. Jones
2010	A*	`conf`	Stochastic computation. DAC Naresh R. Shanbhag, Rami A. Abdallah, Rakesh Kumar, Douglas L. Jones
2010	—	`conf`	Transceiver circuits for optical communications. ISSCC Yuriy M. Greshishchev, Franz Dielacher, Michael Flynn, Donhee Ham, Naresh R. Shanbhag, Takuji Yamamoto
2009	J	`jnl`	Error-resilient low-power Viterbi decoder architectures. IEEE Trans. Signal Process. Rami A. Abdallah, Naresh R. Shanbhag
2009	B	`conf`	Impact of DFE Error Propagation on FEC-Based High-Speed I/O Links. GLOBECOM Rajan Narasimha, Nirmal Warke, Naresh R. Shanbhag
2009	—	`conf`	Low-power implementation of a high-throughput LDPC decoder for IEEE 802.11N standard. SiPS Junho Cho, Naresh R. Shanbhag, Wonyong Sung
2009	—	`conf`	Low-power pre-decoding based viterbi decoder for tail-biting convolutional codes. SiPS Rami A. Abdallah, Seok-Jun Lee, Manish Goel, Naresh R. Shanbhag
2009	—	`conf`	Soft NMR: Exploiting statistics for energy-efficiency. SoC Eric P. Kim, Rami A. Abdallah, Naresh R. Shanbhag
2008	—	`conf`	A 10Gb/s MLSE-based Electronic-Dispersion-Compensation IC with Fast Power-Transient Management for WDM Add/Drop Networks. ISSCC Hyeon-Min Bae, Andrew C. Singer, Jonathan B. Ashbrook, Naresh R. Shanbhag
2008	Misc	`conf`	Computation as estimation: Estimation-theoretic IC design improves robustness and reduces power consumption. ICASSP Shrikanth S. Narayanan, Girish Varatkar, Douglas L. Jones, Naresh R. Shanbhag
2008	J	`jnl`	Electronic dispersion compensation. IEEE Signal Process. Mag. Andrew C. Singer, Naresh R. Shanbhag, Hyeon-Min Bae
2008	J	`jnl`	Error-Resilient Motion Estimation Architecture. IEEE Trans. Very Large Scale Integr. Syst. Girish Varatkar, Naresh R. Shanbhag
2008	—	`conf`	Error-resilient low-power Viterbi decoders via state clustering. SiPS Rami A. Abdallah, Naresh R. Shanbhag
2008	A	`conf`	Error-resilient low-power Viterbi decoders. ISLPED Rami A. Abdallah, Naresh R. Shanbhag
2008	J	`jnl`	Fast Power Transient Management for OC-192 WDM Add/Drop Networks. IEEE J. Solid State Circuits Hyeon-Min Bae, Jonathan B. Ashbrook, Naresh R. Shanbhag, Andrew C. Singer
2008	—	`conf`	Forward error correction for high-speed I/O. ACSCC Rajan Lakshmi Narasimha, Naresh R. Shanbhag
2008	J	`jnl`	Joint Equalization and Coding for On-Chip Bus Communication. IEEE Trans. Very Large Scale Integr. Syst. Srinivasa R. Sridhara, Ganesh Balamurugan, Naresh R. Shanbhag
2008	J	`jnl`	The Search for Alternative Computational Paradigms. IEEE Des. Test Comput. Naresh R. Shanbhag, Subhasish Mitra, Gustavo de Veciana, Michael Orshansky, Radu Marculescu, Jaijeet S. Roychowdhury, Douglas L. Jones, Jan M. Rabaey
2008	—	`conf`	Trends and Challenges in Optical Communications Front-End. ISSCC Yuriy M. Greshishchev, Takuji Yamamoto, Naresh R. Shanbhag
2008	—	`conf`	Trends in energy-efficiency and robustness using stochastic sensor network-on-a-chip. ACM Great Lakes Symposium on VLSI Girish Varatkar, Sriram Narayanan, Naresh R. Shanbhag, Douglas L. Jones
2008	C	`conf`	Variation-tolerant, low-power PN-code acquisition using stochastic sensor NOC. ISCAS Girish Varatkar, Sriram Narayanan, Naresh R. Shanbhag, Douglas L. Jones
2007	J	`jnl`	Coding for Reliable On-Chip Buses: A Class of Fundamental Bounds and Practical Codes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Srinivasa R. Sridhara, Naresh R. Shanbhag
2007	—	`conf`	Sensor Network-On-Chip. SoC Girish Varatkar, Sriram Narayanan, Naresh R. Shanbhag, Douglas L. Jones
2007	—	`conf`	Variation-Tolerant Motion Estimation Architecture. SiPS Girish Varatkar, Naresh R. Shanbhag
2006	J	`jnl`	A 640-Mb/s 2048-bit programmable LDPC decoder chip. IEEE J. Solid State Circuits Mohammad M. Mansour, Naresh R. Shanbhag
2006	J	`jnl`	An MLSE Receiver for Electronic Dispersion Compensation of OC-192 Fiber Links. IEEE J. Solid State Circuits Hyeon-Min Bae, Jonathan B. Ashbrook, Jinki Park, Naresh R. Shanbhag, Andrew C. Singer, Sanjiv Chopra
2006	—	`conf`	An MLSE receiver for electronic-dispersion compensation of OC-192 fiber links. ISSCC Hyeon-Min Bae, Jonathan B. Ashbrook, Jinki Park, Naresh R. Shanbhag, Andrew C. Singer, Sanjiv Chopra
2006	J	`jnl`	Dual-Sampling Skewed CMOS Design for Soft-Error Tolerance. IEEE Trans. Circuits Syst. II Express Briefs Ming Zhang, Naresh R. Shanbhag
2006	A	`conf`	Energy-efficient motion estimation using error-tolerance. ISLPED Girish Varatkar, Naresh R. Shanbhag
2006	J	`jnl`	Energy-efficient soft error-tolerant digital signal processing. IEEE Trans. Very Large Scale Integr. Syst. Byonghyo Shim, Naresh R. Shanbhag
2006	J	`jnl`	Sequential Element Design With Built-In Soft Error Resilience. IEEE Trans. Very Large Scale Integr. Syst. Ming Zhang, Subhasish Mitra, T. M. Mak, Norbert Seifert, Nicholas J. Wang, Quan Shi, Kee Sup Kim, Naresh R. Shanbhag, Sanjay J. Patel
2006	J	`jnl`	Soft-Error-Rate-Analysis (SERA) Methodology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ming Zhang, Naresh R. Shanbhag
2005	J	`jnl`	8-Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation, and clock de-skew. IEEE J. Solid State Circuits James E. Jaussi, Ganesh Balamurugan, David R. Johnson, Bryan Casper, Aaron Martin, Joseph T. Kennedy, Naresh R. Shanbhag, Randy Mooney
2005	J	`jnl`	A 285-MHz pipelined MAP decoder in 0.18-μm CMOS. IEEE J. Solid State Circuits Seok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer
2005	J	`jnl`	A Novel Design Methodology for High-Performance Programmable Decoder Cores for AA-LDPC Codes. J. VLSI Signal Process. Mohammad M. Mansour, Naresh R. Shanbhag
2005	A	`conf`	A low-power bus design using joint repeater insertion and coding. ISLPED Srinivasa R. Sridhara, Naresh R. Shanbhag
2005	—	`conf`	An energy-efficient circuit technique for single event transient noise-tolerance. ISCAS (1) Ming Zhang, Naresh R. Shanbhag
2005	J	`jnl`	Area-efficient high-throughput MAP decoder architectures. IEEE Trans. Very Large Scale Integr. Syst. Seok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer
2005	Misc	`conf`	Coding for Reliable On-Chip Buses: Fundamental Limits and Practical Codes. VLSI Design Srinivasa R. Sridhara, Naresh R. Shanbhag
2005	J	`jnl`	Coding for system-on-chip networks: a unified framework. IEEE Trans. Very Large Scale Integr. Syst. Srinivasa R. Sridhara, Naresh R. Shanbhag
2005	J	`jnl`	Energy Efficient VLSI Architecture for Linear Turbo Equalizer. J. VLSI Signal Process. Seok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer
2005	J	`jnl`	Guest Editorial. J. VLSI Signal Process. Naresh R. Shanbhag, Keshab K. Parhi
2005	—	`conf`	Joint Equalization and Coding for On-Chip Bus Communication. ISQED Srinivasa R. Sridhara, Naresh R. Shanbhag, Ganesh Balamurugan
2005	J	`jnl`	Linear turbo equalization analysis via BER transfer and EXIT charts. IEEE Trans. Signal Process. Seok-Jun Lee, Andrew C. Singer, Naresh R. Shanbhag
2004	A*	`conf`	A communication-theoretic design paradigm for reliable SOCs. DAC Naresh R. Shanbhag
2004	A	`conf`	A soft error rate analysis (SERA) methodology. ICCAD Ming Zhang, Naresh R. Shanbhag
2004	J	`jnl`	A voltage overscaled low-power digital filter IC. IEEE J. Solid State Circuits Rajamohana Hegde, Naresh R. Shanbhag
2004	C	`conf`	Area and Energy-Efficient Crosstalk Avoidance Codes for On-Chip Buses. ICCD Srinivasa R. Sridhara, Arshad Ahmed, Naresh R. Shanbhag
2004	A*	`conf`	Coding for system-on-chip networks: a unified framework. DAC Srinivasa R. Sridhara, Naresh R. Shanbhag
2004	B	`conf`	Reduced complexity interpolation for soft-decoding of reed-solomon codes. ISIT Arshad Ahmed, Ralf Koetter, Naresh R. Shanbhag
2004	J	`jnl`	Reliable and Efficient System-on-Chip Design. Computer Naresh R. Shanbhag
2004	J	`jnl`	Reliable low-power digital signal processing via reduced precision redundancy. IEEE Trans. Very Large Scale Integr. Syst. Byonghyo Shim, Srinivasa R. Sridhara, Naresh R. Shanbhag
2004	—	`conf`	Switching LMS linear turbo equalization. ICASSP (4) Seok-Jun Lee, Andrew C. Singer, Naresh R. Shanbhag
2004	—	`conf`	Switching methods for linear turbo equalization. ISCAS (3) Seok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer
2004	—	`conf`	VLSI architectures for soft-decision decoding of Reed-Solomon codes. ICC Arshad Ahmed, Ralf Koetter, Naresh R. Shanbhag
2003	A	`conf`	A low-power VLSI architecture for turbo decoding. ISLPED Seok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer
2003	B	`conf`	Analysis of linear turbo equalizer via EXIT chart. GLOBECOM Seok-Jun Lee, Andrew C. Singer, Naresh R. Shanbhag
2003	—	`conf`	Architecture-aware low-density parity-check codes. ISCAS (2) Mohammad M. Mansour, Naresh R. Shanbhag
2003	J	`jnl`	Complexity analysis of multicarrier and single-carrier systems for very high-speed digital subscriber line. IEEE Trans. Signal Process. Byonghyo Shim, Naresh R. Shanbhag
2003	J	`jnl`	Energy-efficiency bounds for deep submicron VLSI systems in the presence of noise. IEEE Trans. Very Large Scale Integr. Syst. Lei Wang, Naresh R. Shanbhag
2003	—	`conf`	High bandwidth transimpedance amplifier design using active transmission lines. ISCAS (1) Hyeon-Min Bae, Naresh R. Shanbhag
2003	J	`jnl`	High-throughput LDPC decoders. IEEE Trans. Very Large Scale Integr. Syst. Mohammad M. Mansour, Naresh R. Shanbhag
2003	J	`jnl`	Low-power MIMO signal processing. IEEE Trans. Very Large Scale Integr. Syst. Lei Wang, Naresh R. Shanbhag
2003	J	`jnl`	Low-power filtering via adaptive error-cancellation. IEEE Trans. Signal Process. Lei Wang, Naresh R. Shanbhag
2003	C	`conf`	Modeling and Mitigation of Jitter in Multi-Gbps Source-Synchronous I/O Links. ICCD Ganesh Balamurugan, Naresh R. Shanbhag
2003	—	`conf`	Performance analysis of algorithmic noise-tolerance techniques. ISCAS (4) Byonghyo Shim, Naresh R. Shanbhag
2003	J	`jnl`	VLSI architectures for SISO-APP decoders. IEEE Trans. Very Large Scale Integr. Syst. Mohammad M. Mansour, Naresh R. Shanbhag
2002	J	`jnl`	A 130-nm 6-GHz 256 × 32 bit leakage-tolerant register file. IEEE J. Solid State Circuits Ram K. Krishnamurthy, Atila Alvandpour, Ganesh Balamurugan, Naresh R. Shanbhag, Krishnamurthy Soumyanath, Shekhar Y. Borkar
2002	Misc	`conf`	Design methodology for high-speed iterative decoder architectures. ICASSP Mohammad M. Mansour, Naresh R. Shanbhag
2002	A	`conf`	Low-power VLSI decoder architectures for LDPC codes. ISLPED Mohammad M. Mansour, Naresh R. Shanbhag
2002	A*	`conf`	Reliable and energy-efficient digital signal processing. DAC Naresh R. Shanbhag
2002	—	`conf`	Simplified current and delay models for deep submicron CMOS digital circuits. ISCAS (5) Mohammad M. Mansour, Naresh R. Shanbhag
2002	B	`conf`	Turbo decoder architectures for low-density parity-check codes. GLOBECOM Mohammad M. Mansour, Naresh R. Shanbhag
2001	—	`conf`	A low-power digital filter IC via soft DSP. CICC Rajamohana Hegde, Naresh R. Shanbhag
2001	J	`jnl`	Guest Editorial: Reconfigurable Signal Processing Systems. J. VLSI Signal Process. Wayne P. Burleson, Naresh R. Shanbhag
2001	J	`jnl`	High-speed architectures for Reed-Solomon decoders. IEEE Trans. Very Large Scale Integr. Syst. Dilip V. Sarwate, Naresh R. Shanbhag
2001	—	`conf`	Implementation of a Hermitian decoder IC in 0.35 μm CMOS. CICC Jonathan B. Ashbrook, Naresh R. Shanbhag, Ralf Koetter, Richard E. Blahut
2001	A	`conf`	Low-power AEC-based MIMO signal processing for gigabit ethernet 1000Base-T transceivers. ISLPED Lei Wang, Naresh R. Shanbhag
2001	J	`jnl`	Soft digital signal processing. IEEE Trans. Very Large Scale Integr. Syst. Rajamohana Hegde, Naresh R. Shanbhag
2001	J	`jnl`	The twin-transistor noise-tolerant dynamic circuit technique. IEEE J. Solid State Circuits Ganesh Balamurugan, Naresh R. Shanbhag
2001	J	`jnl`	Total System Energy Minimization for Wireless Image Transmission. J. VLSI Signal Process. Swaroop Appadwedula, Manish Goel, Naresh R. Shanbhag, Douglas L. Jones, Kannan Ramchandran
2000	—	`conf`	A noise-tolerant dynamic circuit design technique. CICC Ganesh Balamurugan, Naresh R. Shanbhag
2000	—	`conf`	Algorithmic noise-tolerance for low-power signal processing in the deep submicron era. EUSIPCO Rajamohana Hegde, Naresh R. Shanbhag
2000	C	`conf`	Architecture driven filter transformations. ISCAS Manish Sharma, Naresh R. Shanbhag
2000	A	`conf`	Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design. ICCAD Ki-Wook Kim, Kwang-Hyun Baek, Naresh R. Shanbhag, C. L. Liu, Sung-Mo Kang
2000	C	`conf`	Energy-efficiency bounds for noise-tolerant dynamic circuits. ISCAS Naresh R. Shanbhag, Lei Wang
2000	—	`conf`	Instruction scheduling for low power on dynamically variable voltage processors. ICECS Mohammad M. Mansour, Makram M. Mansour, Ibrahim N. Hajj, Naresh R. Shanbhag
2000	C	`conf`	Low-power decimation filters for oversampling ADCs via the decorrelating (DECOR) transform. ISCAS Dongwon Seo, Naresh R. Shanbhag, Milton Feng
2000	Misc	`conf`	Low-power digital filtering via soft DSP. ICASSP Rajamohana Hegde, Naresh R. Shanbhag
2000	A	`conf`	Reliable low-power design in the presence of deep submicron noise (embedded tutorial session). ISLPED Naresh R. Shanbhag, Krishnamurthy Soumyanath, Samuel Martin
2000	J	`jnl`	Toward achieving energy efficiency in presence of deep submicron noise. IEEE Trans. Very Large Scale Integr. Syst. Rajamohana Hegde, Naresh R. Shanbhag
1999	J	`jnl`	A coding framework for low-power address and data busses. IEEE Trans. Very Large Scale Integr. Syst. Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj
1999	C	`conf`	A low power data-adaptive motion estimation algorithm. MMSP Jayanto Minocha, Naresh R. Shanbhag
1999	J	`jnl`	A low-power phase-splitting adaptive equalizer for high bit-rate communication systems. IEEE Trans. Signal Process. Rajamohana Hegde, Naresh R. Shanbhag
1999	Misc	`conf`	Analytical Expressions for Power Dissipation of Macro-blocks in DSP Architectures. VLSI Design Sudhakar Bobba, Ibrahim N. Hajj, Naresh R. Shanbhag
1999	J	`jnl`	Dynamic algorithm transformations (DAT)-a systematic approach to low-power reconfigurable signal processing. IEEE Trans. Very Large Scale Integr. Syst. Manish Goel, Naresh R. Shanbhag
1999	J	`jnl`	Dynamic algorithm transforms for low-power reconfigurable adaptive equalizers. IEEE Trans. Signal Process. Manish Goel, Naresh R. Shanbhag
1999	A	`conf`	Energy-efficient dynamic circuit design in the presence of crosstalk noise. ISLPED Ganesh Balamurugan, Naresh R. Shanbhag
1999	A	`conf`	Energy-efficient signal processing via algorithmic noise-tolerance. ISLPED Rajamohana Hegde, Naresh R. Shanbhag
1999	J	`jnl`	Information-theoretic bounds on average signal transition activity [VLSI systems]. IEEE Trans. Very Large Scale Integr. Syst. Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj
1999	Misc	`conf`	Low-power channel coding via dynamic reconfiguration. ICASSP Manish Goel, Naresh R. Shanbhag
1999	—	`conf`	Low-power distributed arithmetic architectures using nonuniform memory partitioning. ISCAS (3) Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj
1999	—	`conf`	Lower bounds on energy dissipation and noise-tolerance for deep submicron VLSI. ISCAS (6) Rajamohana Hegde, Naresh R. Shanbhag
1999	—	`conf`	Noise-tolerant dynamic circuit design. ISCAS (1) Lei Wang, Naresh R. Shanbhag
1998	J	`jnl`	A pipelined adaptive NEXT canceller. IEEE Trans. Signal Process. Gi-Hong Im, Naresh R. Shanbhag
1998	J	`jnl`	Algorithms Transformation Techniques for Low-Power Wireless VLSI Systems Design. Int. J. Wirel. Inf. Networks Naresh R. Shanbhag
1998	Misc	`conf`	Coding for Low-Power Address and Data Busses: A Source-Coding Framework and Applications. VLSI Design Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj
1998	A	`conf`	Decorrelating (DECOR) transformations for low-power adaptive filters. ISLPED Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj
1998	C	`conf`	Efficient wireless image transmission under a total power constraint. MMSP Swaroop Appadwedula, Manish Goel, Douglas L. Jones, Kannan Ramchandran, Naresh R. Shanbhag
1998	A	`conf`	Energy-efficiency in presence of deep submicron noise. ICCAD Rajamohana Hegde, Naresh R. Shanbhag
1998	J	`jnl`	Finite-precision analysis of the pipelined strength-reduced adaptive filter. IEEE Trans. Signal Process. Manish Goel, Naresh R. Shanbhag
1998	Misc	`conf`	Improving the throughput of flexible-precision DSPS via algorithm transformation. ICASSP Manoj Aggarwal, Naresh R. Shanbhag, Narendra Ahuja
1998	Misc	`conf`	Low-power reconfigurable signal processing via dynamic algorithm transformations (DAT). ICASSP Manish Goel, Naresh R. Shanbhag
1998	J	`jnl`	VLSI systems design of 51.84 Mb/s transceivers for ATM-LAN and broadband access. IEEE Trans. Signal Process. Naresh R. Shanbhag, Gi-Hong Im
1997	A	`conf`	Achievable bounds on signal transition activity. ICCAD Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj
1997	A*	`conf`	Analytical Estimation of Transition Activity From Word-Level Signal Statistics. DAC Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj
1997	J	`jnl`	Analytical estimation of signal transition activity from word-level statistics. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj
1997	A	`conf`	Dynamic algorithm transformation (DAT) for low-power adaptive signal processing. ISLPED Manish Goel, Naresh R. Shanbhag
1997	J	`jnl`	Low-power adaptive filter architectures and their application to 51.84 Mb/s ATM-LAN. IEEE Trans. Signal Process. Naresh R. Shanbhag, Manish Goel
1996	A	`conf`	Low-power adaptive filter architectures via strength reduction. ISLPED Manish Goel, Naresh R. Shanbhag
1996	A	`conf`	Lower bounds on power dissipation for DSP algorithms. ISLPED Naresh R. Shanbhag
1996	J	`jnl`	Pipelined adaptive IIR filter architectures using scattered and relaxed look-ahead transformations. IEEE Trans. Signal Process. Naresh R. Shanbhag, Gi-Hong Im
1995	C	`conf`	Pipelined Adaptive IIR Filter Architecture. ISCAS Naresh R. Shanbhag, Gi-Hong Im
1995	J	`jnl`	Pipelined adaptive DFE architectures using relaxed look-ahead. IEEE Trans. Signal Process. Naresh R. Shanbhag, Keshab K. Parhi
1993	C	`conf`	A Pipelined Adaptive Differential Vector Quantizer for Low-power Speech Coding Applications. ISCAS Naresh R. Shanbhag, Keshab K. Parhi
1993	J	`jnl`	A pipelined adaptive lattice filter architecture. IEEE Trans. Signal Process. Naresh R. Shanbhag, Keshab K. Parhi
1993	C	`conf`	Roundoff error analysis of the pipelined ADPCM coder. ISCAS Naresh R. Shanbhag, Keshab K. Parhi
1991	J	`jnl`	A single-chip pipelined 2-D FIR filter using residue arithmetic. IEEE J. Solid State Circuits Naresh R. Shanbhag, Raymond E. Siferd
1991	J	`jnl`	An improved systolic architecture for 2-D digital filters. IEEE Trans. Signal Process. Naresh R. Shanbhag
1990	J	`jnl`	Quaternary logic circuits in 2- mu m CMOS technology. IEEE J. Solid State Circuits Naresh R. Shanbhag, Dipankar Nagchoudhuri, Raymond E. Siferd, Gangaikondan S. Visweswaran
1988	J	`jnl`	Parallel implementation of a 4*4-bit multiplier using a modified Booth's algorithm. IEEE J. Solid State Circuits Naresh R. Shanbhag, Pushkal Juneja