Narendra V. Shenoy

35 papers A* 8A 9C 4Misc 4Journal 5Unranked 5

Year	Rank	Type	Title / Venue / Authors
2008	—	`conf`	Cell Swapping Based Migration Methodology for Analog and Custom Layouts. ISQED Shabbir H. Batterywala, Sambuddha Bhattacharya, Subramanian Rajagopalan, Hi-Keung Tony Ma, Narendra V. Shenoy
2008	—	`conf`	On Efficient and Robust Constraint Generation for Practical Layout Legalization. ISQED Sambuddha Bhattacharya, Shabbir H. Batterywala, Subramanian Rajagopalan, Hi-Keung Tony Ma, Narendra V. Shenoy
2007	J	`jnl`	Advances in Computation of the Maximum of a Set of Gaussian Random Variables. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Debjit Sinha, Hai Zhou, Narendra V. Shenoy
2007	Misc	`conf`	Impact of Modern Process Technologies on the Electrical Parameters of Interconnects. VLSI Design Debjit Sinha, Jianfeng Luo, Subramanian Rajagopalan, Shabbir H. Batterywala, Narendra V. Shenoy, Hai Zhou
2006	—	`conf`	Advances in Computation of the Maximum of a Set of Random Variables. ISQED Debjit Sinha, Hai Zhou, Narendra V. Shenoy
2006	J	`jnl`	Statistical Timing Yield Optimization by Gate Sizing. IEEE Trans. Very Large Scale Integr. Syst. Debjit Sinha, Narendra V. Shenoy, Hai Zhou
2005	A	`conf`	Statistical gate sizing for timing yield optimization. ICCAD Debjit Sinha, Narendra V. Shenoy, Hai Zhou
2004	Misc	`conf`	Computing Silent Gate Models for Noise Analysis from Slew and Delay Tables. VLSI Design Shabbir H. Batterywala, Narendra V. Shenoy
2004	A*	`conf`	Design automation for mask programmable fabrics. DAC Narendra V. Shenoy, Jamil Kawa, Raul Camposano
2003	Misc	`conf`	A Method to Estimate Slew and Delay in Coupled Digital Circuits. VLSI Design Shabbir H. Batterywala, Narendra V. Shenoy
2003	A*	`conf`	Emerging markets: design goes global. DAC Chi-Foon Chan, Deirdre Hanford, Jian Yue Pan, Narendra V. Shenoy, Mahesh Mehendale, A. Vasudevan, Shaojun Wei
2002	C	`conf`	An Efficient External-Memory Implementation of Region Query with Application to Area Routing. ICCD Stan Y. Liao, Narendra V. Shenoy, William Nicholls
2002	A*	`conf`	An efficient routing database. DAC Narendra V. Shenoy, William Nicholls
2002	J	`jnl`	Efficient minimum spanning tree construction without Delaunay triangulation. Inf. Process. Lett. Hai Zhou, Narendra V. Shenoy, William Nicholls
2002	A	`conf`	Track assignment: a desirable intermediate step between global routing and detailed routing. ICCAD Shabbir H. Batterywala, Narendra V. Shenoy, William Nicholls, Hai Zhou
2001	—	`conf`	Efficient minimum spanning tree construction without Delaunay triangulation. ASP-DAC Hai Zhou, Narendra V. Shenoy, William Nicholls
2001	A*	`conf`	Timing Analysis with Crosstalk as Fixpoints on Complete Lattice. DAC Hai Zhou, Narendra V. Shenoy, William Nicholls
1999	C	`conf`	A Robust Solution to the Timing Convergence Problem in High-Performance Design. ICCD Narendra V. Shenoy, Mahesh A. Iyer, Robert F. Damiano, Kevin Harer, Hi-Keung Tony Ma, Paul Thilking
1997	C	`conf`	Discrete Drive Selection for Continuous Sizing. ICCD Ramsey W. Haddad, Lukas P. P. P. van Ginneken, Narendra V. Shenoy
1997	J	`jnl`	Retiming: Theory and practice. Integr. Narendra V. Shenoy
1997	—	`conf`	The future of logic synthesis and physical design in deep-submicron process geometries. ISPD Kurt Keutzer, A. Richard Newton, Narendra V. Shenoy
1996	A	`conf`	Embedded tutorial: Speed - new paradigms in design for performance. ICCAD Ralph H. J. M. Otten, Lukas P. P. P. van Ginneken, Narendra V. Shenoy
1995	Misc	`conf`	Functional clock schedule optimization. VLSI Design Alexander Saldanha, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1994	A	`conf`	Efficient implementation of retiming. ICCAD Narendra V. Shenoy, Richard L. Rudell
1994	J	`jnl`	Linear programming for hazard elimination in asynchronous circuits. J. VLSI Signal Process. Luciano Lavagno, Narendra V. Shenoy, Alberto L. Sangiovanni-Vincentelli
1993	A*	`conf`	A Verification Technique for Gated Clock. DAC Masamichi Kawarabayashi, Narendra V. Shenoy, Alberto L. Sangiovanni-Vincentelli
1993	A	`conf`	Minimum padding to satisfy short path constraints. ICCAD Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1993	A*	`conf`	Resynthesis of Multi-Phase Pipelines. DAC Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1992	A	`conf`	Graph algorithms for clock schedule optimization. ICCAD Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1992	A*	`conf`	On the Temporal Equivalence of Sequential Circuits. DAC Narendra V. Shenoy, Kanwar Jit Singh, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1992	A	`conf`	Verifying clock schedules. ICCAD Thomas G. Szymanski, Narendra V. Shenoy
1991	A	`conf`	Improved Logic Synthesis Algorithms for Table Look Up Architectures. ICCAD Rajeev Murgai, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1991	A	`conf`	Performance Directed Synthesis for Table Look Up Programmable Gate Arrays. ICCAD Rajeev Murgai, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1991	C	`conf`	Retiming of Circuits with Single Phase Transparent Latches. ICCD Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1990	A*	`conf`	Logic Synthesis for Programmable Gate Arrays. DAC Rajeev Murgai, Yoshihito Nishizaki, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli