Naoya Watanabe

29 papers A* 1C 1Journal 12Unranked 15

Year	Rank	Type	Title / Venue / Authors
2021	J	`jnl`	Analysis and evaluation of noise coupling between through-silicon-vias. IEICE Electron. Express Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi
2021	J	`jnl`	Landside capacitor efficacy among multi-chip-module using Si-interposer. IEICE Electron. Express Yuuki Araga, Ryo Kasai, Daisuke Tanaka, Yoshihide Murakami, Kyoshi Mihara, Kazuo Makida, Hiroki Sonoda, Makoto Nagata, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi
2020	J	`jnl`	Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices. IEEE J. Solid State Circuits Takuji Miki, Makoto Nagata, Hiroki Sonoda, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi
2019	—	`conf`	A Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices. A-SSCC Takuji Miki, Makoto Nagata, Hiroki Sonoda, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi
2019	—	`conf`	Over-the-top Si Interposer Embedding Backside Buried Metal PDN to Reduce Power Supply Impedance of Large Scale Digital ICs. 3DIC Takuji Miki, Makoto Nagata, Akihiro Tsukioka, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi
2019	—	`conf`	Thermal Stress Comparison of Annular-Trench-Isolated (ATI) TSV with Cu and Solder Core. 3DIC Wei Feng, Naoya Watanabe, Haruo Shimamoto, Masahiro Aoyagi, Katsuya Kikuchi
2017	J	`jnl`	Thermal impact of extreme die thinning in bump-bonded three-dimensional integrated circuits. Microelectron. Reliab. Samson Melamed, Naoya Watanabe, Shunsuke Nemoto, Haruo Shimamoto, Katsuya Kikuchi, Masahiro Aoyagi
2016	J	`jnl`	Fabrication and stress analysis of annular-trench-isolated TSV. Microelectron. Reliab. Wei Feng, Tung Thanh Bui, Naoya Watanabe, Haruo Shimamoto, Masahiro Aoyagi, Katsuya Kikuchi
2016	J	`jnl`	Impact of thinning stacked dies on the thermal resistance of bump-bonded three-dimensional integrated circuits. Microelectron. Reliab. Samson Melamed, Naoya Watanabe, Shunsuke Nemoto, Haruo Shimamoto, Katsuya Kikuchi, Masahiro Aoyagi
2016	J	`jnl`	Validation of TSV thermo-mechanical simulation by stress measurement. Microelectron. Reliab. Wei Feng, Naoya Watanabe, Haruo Shimamoto, Masahiro Aoyagi, Katsuya Kikuchi
2016	—	`conf`	Wet cleaning process for high-yield via-last TSV formation. 3DIC Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi, Masahiro Aoyagi, Hidekazu Kikuchi, Azusa Yanagisawa, Akio Nakamura
2015	—	`conf`	Twice-etched silicon approach for via-last through-silicon-via with a Parylene-HT liner. 3DIC Tung Thanh Bui, Naoya Watanabe, Masahiro Aoyagi, Katsuya Kikuchi
2014	—	`conf`	13.6 A 28nm 400MHz 4-parallel 1.6Gsearch/s 80Mb ternary CAM. ISSCC Koji Nii, Teruhiko Amano, Naoya Watanabe, Minoru Yamawaki, Kenji Yoshinaga, Mihoko Wada, Isamu Hayashi
2014	—	`conf`	Analysis of thermal stress distribution for TSV with novel structure. 3DIC Wei Feng, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi, Masahiro Aoyagi
2014	—	`conf`	Copper filled TSV formation with Parylene-HT insulator for low-temperature compatible 3D integration. 3DIC Bui Thanh Tung, Xiaojin Cheng, Naoya Watanabe, Fumiki Kato, Katsuya Kikuchi, Masahiro Aoyagi
2014	—	`conf`	Small-diameter TSV reveal process using direct Si/Cu grinding and metal contamination removal. 3DIC Naoya Watanabe, Masahiro Aoyagi, Daisuke Katagawa, Tsubasa Bandoh, Takahiko Mitsui, Eiichi Yamamoto
2013	J	`jnl`	A 250-MHz 18-Mb Full Ternary CAM With Low-Voltage Matchline Sensing Scheme in 65-nm CMOS. IEEE J. Solid State Circuits Isamu Hayashi, Teruhiko Amano, Naoya Watanabe, Yuji Yano, Yasuto Kuroda, M. Shirata, Katsumi Dosaka, Koji Nii, Hideyuki Noda, Hiroyuki Kawai
2013	—	`conf`	New optical three dimensional structure measurement method of cone shape micro bumps used for 3D LSI chip stacking. 3DIC Masahiro Aoyagi, Naoya Watanabe, Motohiro Suzuki, Katsuya Kikuchi, Shunsuke Nemoto, Noriaki Arima, Misaki Ishizuka, Koji Suzuki, Toshio Shiomi
2011	—	`conf`	Damage evaluation of wet-chemical silicon-wafer thinning process. 3DIC Naoya Watanabe, Takumi Miyazaki, Masahiro Aoyagi, Kazuhiro Yoshikawa
2011	—	`conf`	High frequency signal transmission characteristics of cone bump interconnections. 3DIC Akihiro Ikeda, Naoya Watanabe, Tanemasa Asano
2011	—	`conf`	Low-temperature bonding of LSI chips to PEN film using Au cone bump for heterogeneous integration. 3DIC Takanori Shuto, Naoya Watanabe, Akihiro Ikeda, Tanemasa Asano
2011	—	`conf`	PDN impedance analysis of TSV-decoupling capacitor embedded Silicon interposer for 3D-integrated CMOS image sensor system. 3DIC Katsuya Kikuchi, Chihiro Ueda, Fumiaki Fujii, Yutaka Akiyama, Naoya Watanabe, Yasuhiro Kitamura, Toshio Gomyo, Toshikazu Okubo, Tetsuya Koyama, Tadashi Kamada, Masahiro Aoyagi, Kanji Otsuka
2005	J	`jnl`	A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros. IEICE Trans. Electron. Akira Yamazaki, Fukashi Morishita, Naoya Watanabe, Teruhiko Amano, Masaru Haraguchi, Hideyuki Noda, Atsushi Hachisuka, Katsumi Dosaka, Kazutami Arimoto, Setsuo Wake, Hideyuki Ozaki, Tsutomu Yoshihara
1999	J	`jnl`	Source-synchronization and timing vernier techniques for 1.2-GB/s SLDRAM interface. IEEE J. Solid State Circuits Yasunobu Nakase, Yoshikazu Morooka, David J. Perlman, Daniel J. Kolor, Jae-Myoung Choi, Hyun J. Shin, Tsutomu Yoshimura, Naoya Watanabe, Yoshio Matsuda, Masaki Kumanoya, Michihiro Yamada
1996	J	`jnl`	A 90-MHz 16-Mb system integrated memory with direct interface to CPU. IEEE J. Solid State Circuits Katsumi Dosaka, Akira Yamazaki, Naoya Watanabe, Hideaki Abe, Jun Ohtani, Toshiyuki Ogawa, Kazunori Ishihara, Masaki Kumanoya
1991	J	`jnl`	Evaluation of the Effects of Protocol Processing Overhead in Error Recovery Schemes for a High-Speed Packet Switched Network: Link-by-Link versus Edge-to-Edge Schemes. IEEE J. Sel. Areas Commun. Jaime Jungok Bae, Tatsuya Suda, Naoya Watanabe
1988	A*	`conf`	Evaluation of error recovery schemes for a high-speed packet switched network: link-by-link versus edge-to-edge schemes. INFOCOM Tatsuya Suda, Naoya Watanabe
1986	C	`conf`	Multicast Communication Facilities in a High Speed Packet Switching Network. ICCC Ken-ichi Yukimatsu, Naoya Watanabe, Takashi Honda
1986	—	`conf`	Network Testing for Digital Data Networks. ICC Naoya Watanabe, Ken-ichi Yukimatsu, Toshiaki Doi, Masachika Ishizura, Etsugo Yoneda, Makoto Kawashima, Kazuhiro Hayashi