Naoya Torii

20 papers A* 1A 3B 1C 2Misc 2Journal 7Unranked 4
YearRankTypeTitle / Venue / Authors
2022 J jnl
Implementation and Evaluation of Ring Oscillator-based True Random Number Generator.
Int. J. Netw. Comput.
Naoya Torii, Ryuichi Minagawa, Hideaki Kevin Omae, Kotaro Hayashi
2022 — conf
Side-channel attack on COSO-based TRNG to estimate output bits.
CANDARW
Kotaro Hayashi, Ryuichi Minagawa, Naoya Torii
2021 — conf
Implementation and Evaluation of Ring Oscillator-based True Random Number Generator.
CANDAR
Naoya Torii, Ryuichi Minagawa, Hideaki Kevin Omae, Kotaro Hayashi
2016 J jnl
ASIC implementation of random number generators using SR latches and its evaluation.
EURASIP J. Inf. Secur.
Naoya Torii, Hirotaka Kokubo, Dai Yamamoto, Kouichi Itoh, Masahiko Takenaka, Tsutomu Matsumoto
2016 — conf
Evaluation of Latch-Based PUFs Implemented on 40 nm ASICs.
CANDAR
Naoya Torii, Dai Yamamoto, Tsutomu Matsumoto
2016 — conf
Evaluation of Latch-based Physical Random Number Generator Implementation on 40 nm ASICs.
TrustED@CCS
Naoya Torii, Dai Yamamoto, Tsutomu Matsumoto
2016 J jnl
Experimental Evaluation on the Resistance of Latch PUFs Implemented on ASIC against FIB-Based Invasive Attacks.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Naoya Torii, Dai Yamamoto, Masahiko Takenaka, Tsutomu Matsumoto
2015 J jnl
A new method for enhancing variety and maintaining reliability of PUF responses and its evaluation on ASICs.
J. Cryptogr. Eng.
Dai Yamamoto, Kazuo Sakiyama, Mitsugu Iwamoto, Kazuo Ohta, Masahiko Takenaka, Kouichi Itoh, Naoya Torii
2014 B conf
A Spoofing Attack against a Cancelable Biometric Authentication Scheme.
AINA
Tetsuya Izu, Yumi Sakemi, Masahiko Takenaka, Naoya Torii
2014 Misc conf
A Technique Using PUFs for Protecting Circuit Layout Designs against Reverse Engineering.
IWSEC
Dai Yamamoto, Masahiko Takenaka, Kazuo Sakiyama, Naoya Torii
2014 J jnl
Dynamic Behavior of RS latches using FIB processing and probe connection.
IACR Cryptol. ePrint Arch.
Naoya Torii, Dai Yamamoto, Masahiko Takenaka, Tsutomu Matsumoto
2014 C conf
Security Evaluation of Bistable Ring PUFs on FPGAs using Differential and Linear Analysis.
FedCSIS
Dai Yamamoto, Masahiko Takenaka, Kazuo Sakiyama, Naoya Torii
2013 C conf
Evaluation of ASIC Implementation of Physical Random Number Generators Using RS Latches.
CARDIS
Hirotaka Kokubo, Dai Yamamoto, Masahiko Takenaka, Kouichi Itoh, Naoya Torii
2012 J jnl
Foreword.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Naoya Torii
2005 J jnl
Design Optimization of a High-Speed, Area-Efficient and Low-Power Montgomery Modular Multiplier for RSA Algorithm.
IEICE Trans. Electron.
Shoichi Masui, Kenji Mukaida, Masahiko Takenaka, Naoya Torii
2002 A conf
DPA Countermeasures by Improving the Window Method.
CHES
Kouichi Itoh, Jun Yajima, Masahiko Takenaka, Naoya Torii
2001 Misc conf
DPA Countermeasure Based on the "Masking Method".
ICISC
Kouichi Itoh, Masahiko Takenaka, Naoya Torii
2001 A* conf
The Block Cipher SC2000.
FSE
Takeshi Shimoyama, Hitoshi Yanami, Kazuhiro Yokoyama, Masahiko Takenaka, Kouichi Itoh, Jun Yajima, Naoya Torii, Hidema Tanaka
2000 A conf
Implementation of Elliptic Curve Cryptographic Coprocessor over GF(2
CHES
Souichi Okada, Naoya Torii, Kouichi Itoh, Masahiko Takenaka
1999 A conf
Fast Implementation of Public-Key Cryptography ona DSP TMS320C6201.
CHES
Kouichi Itoh, Masahiko Takenaka, Naoya Torii, Syouji Temma, Yasushi Kurihara