Naoya Onizawa

127 papers A* 1A 3C 8Misc 3Journal 64Unranked 48
YearRankTypeTitle / Venue / Authors
2026 J jnl
Analog-to-Stochastic Converter Using Magnetic Tunnel Junction Devices for Vision Chips.
CoRR
Naoya Onizawa, Daisaku Katagiri, Warren J. Gross, Takahiro Hanyu
2026 J jnl
Bit-Width-Aware Design Environment for Few-Shot Learning on Edge AI Hardware.
CoRR
R. Kanda, Hugo Le Blevec, Naoya Onizawa, Mathieu Léonardon, Vincent Gripon, Takahiro Hanyu
2026 J jnl
Design Environment of Quantization-Aware Edge AI Hardware for Few-Shot Learning.
CoRR
R. Kanda, Naoya Onizawa, Mathieu Léonardon, Vincent Gripon, Takahiro Hanyu
2026 J jnl
Efficient CMOS Invertible Logic Using Stochastic Computing.
CoRR
Sean C. Smithson, Naoya Onizawa, Brett H. Meyer, Warren J. Gross, Takahiro Hanyu
2026 J jnl
Efficient Few-Shot Learning for Edge AI via Knowledge Distillation on MobileViT.
CoRR
Shuhei Tsuyuki, Reda Bensaid, Jérémy Morlier, Mathieu Léonardon, Naoya Onizawa, Vincent Gripon, Takahiro Hanyu
2026 J jnl
Energy-Efficient p-Bit-Based Fully-Connected Quantum-Inspired Simulated Annealer with Dual BRAM Architecture.
CoRR
Naoya Onizawa, Taiga Kubuta, Duckgyu Shin, Takahiro Hanyu
2026 J jnl
Energy-Efficient p-bit-Based Fully-Connected Quantum-Inspired Simulated Annealer With Dual BRAM Architecture.
IEEE Access
Naoya Onizawa, Taiga Kubuta, Duckgyu Shin, Takahiro Hanyu
2026 J jnl
Enhanced Convergence in p-bit Based Simulated Annealing with Partial Deactivation for Large-Scale Combinatorial Optimization Problems.
CoRR
Naoya Onizawa, Takahiro Hanyu
2026 J jnl
GPU-accelerated simulated annealing based on p-bits with real-world device-variability modeling.
CoRR
Naoya Onizawa, Takahiro Hanyu
2026 J jnl
High Convergence Rates of CMOS Invertible Logic Circuits Based on Many-Body Hamiltonians.
CoRR
Naoya Onizawa, Takahiro Hanyu
2026 J jnl
Memory-Efficient FPGA Implementation of Stochastic Simulated Annealing.
CoRR
Duckgyu Shin, Naoya Onizawa, Warren J. Gross, Takahiro Hanyu
2025 C conf
Bit-Width-Aware Design Environment for Few-Shot Learning on Edge AI Hardware.
ISCAS
R. Kanda, Hugo Le Blevec, Naoya Onizawa, Mathieu Léonardon, Vincent Gripon, Takahiro Hanyu
2025 — conf
Generating Hamiltonians with Known Minimum Energy Based on Ground-State Spin Logic for Probabilistic-Bit-Based Simulated Annealing.
ISMVL
Naoya Onizawa, Takahiro Hanyu
2024 — conf
Design Environment of Quantization-Aware Edge AI Hardware for Few-Shot Learning.
MWSCAS
R. Kanda, Naoya Onizawa, Mathieu Léonardon, Vincent Gripon, Takahiro Hanyu
2024 J jnl
Stochastic Simulated Quantum Annealing for Fast Solution of Combinatorial Optimization Problems.
IEEE Access
Naoya Onizawa, Ryoma Sasaki, Duckgyu Shin, Warren J. Gross, Takahiro Hanyu
2023 J jnl
Fast-Converging Simulated Annealing for Ising Models Based on Integral Stochastic Computing.
IEEE Trans. Neural Networks Learn. Syst.
Naoya Onizawa, Kota Katsuki, Duckgyu Shin, Warren J. Gross, Takahiro Hanyu
2023 — conf
Improving Stochastic Quantum-Like Annealing Based on Rerandomization.
ICECS
Ryoma Sasaki, Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu
2023 J jnl
Local Energy Distribution Based Hyperparameter Determination for Stochastic Simulated Annealing.
CoRR
Naoya Onizawa, Kyo Kuroki, Duckgyu Shin, Takahiro Hanyu
2023 J jnl
Memory-Efficient FPGA Implementation of Stochastic Simulated Annealing.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Duckgyu Shin, Naoya Onizawa, Warren J. Gross, Takahiro Hanyu
2023 J jnl
Self-Adaptive Gate Control for Efficient Escape From Local Minimum Energy on Invertible Logic.
IEEE Access
Naoya Onizawa, Koji Yano, Seiichi Shin, Hiroyuki Fujita, Takahiro Hanyu
2023 — conf
Stochastic Implementation of Simulated Quantum Annealing on PYNQ.
ICFPT
Taiga Kubuta, Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu
2023 J jnl
Stochastic Quantum Monte Carlo Algorithm for Large-Scale Combinatorial Optimization Problems.
CoRR
Naoya Onizawa, Ryoma Sasaki, Duckgyu Shin, Warren J. Gross, Takahiro Hanyu
2022 — conf
Fast Solving Complete 2000-Node Optimization Using Stochastic-Computing Simulated Annealing.
ICECS 2022
Kota Katsuki, Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu
2022 J jnl
Implementation of CMOS Invertible Logic on Zynq-SoC Platform: A Case Study of Training BNN.
FLAP
Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu
2021 J jnl
A Design Framework for Invertible Logic.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Naoya Onizawa, Kaito Nishino, Sean C. Smithson, Brett H. Meyer, Warren J. Gross, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu
2021 J jnl
Hardware Acceleration of Large-Scale CMOS Invertible Logic Based on Sparse Hamiltonian Matrices.
IEEE Open J. Circuits Syst.
Naoya Onizawa, Akira Tamakoshi, Takahiro Hanyu
2021 C conf
High Convergence Rates of CMOS Invertible Logic Circuits Based on Many-Body Hamiltonians.
ISCAS
Naoya Onizawa, Takahiro Hanyu
2021 J jnl
Multi-Context TCAM-Based Selective Computing: Design Space Exploration for a Low-Power NN.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ren Arakawa, Naoya Onizawa, Jean-Philippe Diguet, Takahiro Hanyu
2021 — conf
Scalable Hardware Architecture for Invertible Logic with Sparse Hamiltonian Matrices.
SiPS
Naoya Onizawa, Akira Tamakoshi, Takahiro Hanyu
2021 J jnl
Sparse Random Signals for Fast Convergence on Invertible Logic.
IEEE Access
Naoya Onizawa, Makoto Kato, Hitoshi Yamagata, Koji Yano, Seiichi Shin, Hiroyuki Fujita, Takahiro Hanyu
2020 J jnl
Design Automation of Invertible Logic Circuit from a Standard HDL Description.
FLAP
Makoto Kato, Naoya Onizawa, Takahiro Hanyu
2020 — conf
Design of an Energy-Efficient True Random Number Generator Based on Triple Read-Write Data-Stream Multiplexing of MTJ Devices.
NEWCAS
Akira Tamakoshi, Naoya Onizawa, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu
2020 J jnl
Design of an MTJ-based Nonvolatile Multi-context Ternary Content-addressable Memory.
FLAP
Naoya Onizawa, Ren Arakawa, Takahiro Hanyu
2020 J jnl
Fast Hardware-based Learning Algorithm for Binarized Perceptrons using CMOS Invertible Logic.
FLAP
Naoya Onizawa, Duckgyu Shin, Takahiro Hanyu
2020 J jnl
High-Throughput/Low-Energy MTJ-Based True Random Number Generator Using a Multi-Voltage/Current Converter.
IEEE Trans. Very Large Scale Integr. Syst.
Naoya Onizawa, Shogo Mukaida, Akira Tamakoshi, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu
2020 J jnl
In-Hardware Training Chip Based on CMOS Invertible Logic for Machine Learning.
IEEE Trans. Circuits Syst. I Fundam. Theory Appl.
Naoya Onizawa, Sean C. Smithson, Brett H. Meyer, Warren J. Gross, Takahiro Hanyu
2020 J jnl
Memristive Computational Memory Using Memristor Overwrite Logic (MOL).
IEEE Trans. Very Large Scale Integr. Syst.
Khaled Alhaj Ali, Mostafa Rizk, Amer Baghdadi, Jean-Philippe Diguet, Jalal Jomaah, Naoya Onizawa, Takahiro Hanyu
2020 J jnl
Training Hardware for Binarized Convolutional Neural Network Based on CMOS Invertible Logic.
IEEE Access
Duckgyu Shin, Naoya Onizawa, Warren J. Gross, Takahiro Hanyu
2019 Misc conf
A Design Framework for Invertible Logic.
ACSSC
Naoya Onizawa, Kaito Nishino, Sean C. Smithson, Brett H. Meyer, Warren J. Gross, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu
2019 J jnl
Efficient CMOS Invertible Logic Using Stochastic Computing.
IEEE Trans. Circuits Syst. I Regul. Pap.
Sean C. Smithson, Naoya Onizawa, Brett H. Meyer, Warren J. Gross, Takahiro Hanyu
2019 — conf
FPGA Implementation of Binarized Perceptron Learning Hardware Using CMOS Invertible Logic.
ICECS
Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu
2019 — conf
Multi-Context TCAM Based Selective Computing Architecture for a Low-Power NN.
ICECS
Ren Arakawa, Naoya Onizawa, Jean-Philippe Diguet, Takahiro Hanyu
2019 — conf
Stochastic-Computing Based Brainwave LSI Towards an Intelligence Edge.
ICECS
Naoya Onizawa, Warren J. Gross, Takahiro Hanyu
2018 J jnl
A Generalized Stochastic Implementation of the Disparity Energy Model for Depth Perception.
J. Signal Process. Syst.
Kaushik Boga, François Leduc-Primeau, Naoya Onizawa, Kazumichi Matsumiya, Takahiro Hanyu, Warren J. Gross
2018 J jnl
An Accuracy/Energy-Flexible Configurable Gabor-Filter Chip Based on Stochastic Computation With Dynamic Voltage-Frequency-Length Scaling.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Naoya Onizawa, Daisaku Katagiri, Kazumichi Matsumiya, Warren J. Gross, Takahiro Hanyu
2018 — conf
Design of a Low-Power MTJ-Based True Random Number Generator Using a Multi-voltage/Current Converter.
ISMVL
Shogo Mukaida, Naoya Onizawa, Takahiro Hanyu
2018 C conf
High-Precision Stochastic State-Space Digital Filters Based on Minimum Roundoff Noise Structure.
ISCAS
Shunsuke Koshita, Naoya Onizawa, Masahide Abe, Takahiro Hanyu, Masayuki Kawamata
2018 J jnl
MTJ-based asynchronous circuits for Re-initialization free computing against power failures.
Microelectron. J.
Naoya Onizawa, Masashi Imai, Tomohiro Yoneda, Takahiro Hanyu
2018 J jnl
Networked Power-Gated MRAMs for Memory-Based Computing.
IEEE Trans. Very Large Scale Integr. Syst.
Jean-Philippe Diguet, Naoya Onizawa, Mostafa Rizk, Martha Johanna Sepúlveda, Amer Baghdadi, Takahiro Hanyu
2018 — conf
Study of Stochastic Invertible Multiplier Designs.
ICECS
Kaito Nishino, Sean C. Smithson, Naoya Onizawa, Brett H. Meyer, Warren J. Gross, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu
2017 — conf
Accuracy/energy-flexible stochastic configurable 2D Gabor filter with instant-on capability.
ESSCIRC
Naoya Onizawa, Kazumichi Matsumiya, Warren J. Gross, Takahiro Hanyu
2017 J jnl
Area/Energy-Efficient Gammatone Filters Based on Stochastic Computation.
IEEE Trans. Very Large Scale Integr. Syst.
Naoya Onizawa, Shunsuke Koshita, Shuichi Sakamoto, Masahide Abe, Masayuki Kawamata, Takahiro Hanyu
2017 — conf
Design of stochastic asymmetric compensation filters for auditory signal processing.
GlobalSIP
Naoya Onizawa, Shunsuke Koshita, Shuichi Sakamoto, Masayuki Kawamata, Takahiro Hanyu
2017 — conf
Evaluation of Stochastic Cascaded IIR Filters.
ISMVL
Naoya Onizawa, Shunsuke Koshita, Shuichi Sakamoto, Masayuki Kawamata, Takahiro Hanyu
2017 J jnl
High-Accuracy and Area-Efficient Stochastic FIR Digital Filters Based on Hybrid Computation.
IEICE Trans. Inf. Syst.
Shunsuke Koshita, Naoya Onizawa, Masahide Abe, Takahiro Hanyu, Masayuki Kawamata
2017 — conf
MTJ-based Asynchronous Circuits for Re-initialization Free Computing against Power Failures.
ASYNC
Naoya Onizawa, Masashi Imai, Takahiro Hanyu, Tomohiro Yoneda
2017 — conf
NoC-MRAM architecture for memory-based computing: Database-search case study.
NEWCAS
Mostafa Rizk, Jean-Philippe Diguet, Naoya Onizawa, Amer Baghdadi, Martha Johanna Sepúlveda, Y. Akgul, Vincent Gripon, Takahiro Hanyu
2017 J jnl
Sudden Power-Outage Resilient In-Processor Checkpointing for Energy-Harvesting Nonvolatile Processors.
IEEE Trans. Emerg. Top. Comput.
Naoya Onizawa, Akira Mochizuki, Akira Tamakoshi, Takahiro Hanyu
2017 A conf
Three-terminal MTJ-based nonvolatile logic circuits with self-terminated writing mechanism for ultra-low-power VLSI processor.
DATE
Takahiro Hanyu, Daisuke Suzuki, Naoya Onizawa, Masanori Natsui
2017 J jnl
VLSI Implementation of Deep Neural Network Using Integral Stochastic Computing.
IEEE Trans. Very Large Scale Integr. Syst.
Arash Ardakani, François Leduc-Primeau, Naoya Onizawa, Takahiro Hanyu, Warren J. Gross
2016 J jnl
Evaluation of Soft-Delay-Error Effects in Content-Addressable Memory.
J. Multiple Valued Log. Soft Comput.
Naoya Onizawa, Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Takahiro Hanyu
2016 Misc conf
Gammatone filter based on stochastic computation.
ICASSP
Naoya Onizawa, Shunsuke Koshita, Shuichi Sakamoto, Masahide Abe, Masayuki Kawamata, Takahiro Hanyu
2016 J jnl
Hardware Implementation of Associative Memories Based on Multiple-Valued Sparse Clustered Networks.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Naoya Onizawa, Hooman Jarollahi, Takahiro Hanyu, Warren J. Gross
2016 — conf
Realization of FIR Digital Filters Based on Stochastic/Binary Hybrid Computation.
ISMVL
Shunsuke Koshita, Naoya Onizawa, Masahide Abe, Takahiro Hanyu, Masayuki Kawamata
2016 — conf
Redundant STT-MTJ-based nonvolatile flip-flops for low write-error-rate operations.
NEWCAS
Naoya Onizawa, Takahiro Hanyu
2016 J jnl
Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing.
Proc. IEEE
Takahiro Hanyu, Tetsuo Endoh, Daisuke Suzuki, Hiroki Koike, Yitao Ma, Naoya Onizawa, Masanori Natsui, Shoji Ikeda, Hideo Ohno
2016 — conf
VLSI implementation of deep neural networks using integral stochastic computing.
ISTC
Arash Ardakani, François Leduc-Primeau, Naoya Onizawa, Takahiro Hanyu, Warren J. Gross
2015 — conf
A sudden power-outage resilient nonvolatile microprocessor for immediate system recovery.
NANOARCH
Naoya Onizawa, Akira Mochizuki, Akira Tamakoshi, Takahiro Hanyu
2015 J jnl
Algorithm and Architecture for a Low-Power Content-Addressable Memory Based on Sparse Clustered Networks.
IEEE Trans. Very Large Scale Integr. Syst.
Hooman Jarollahi, Vincent Gripon, Naoya Onizawa, Warren J. Gross
2015 — conf
Design of an STT-MTJ based true random number generator using digitally controlled probability-locked loop.
NEWCAS
Satoshi Oosawa, Takayuki Konishi, Naoya Onizawa, Takahiro Hanyu
2015 — conf
Early-Stage Operation-Skipping Scheme for Low-Power Stochastic Image Processors.
ISMVL
Daisaku Katagiri, Naoya Onizawa, Takahiro Hanyu
2015 — conf
Frequency-flexible stochastic Gabor filter.
DSP
Naoya Onizawa, Daisaku Katagiri, Kazumichi Matsumiya, Warren J. Gross, Takahiro Hanyu
2015 J jnl
Gabor Filter Based on Stochastic Computation.
IEEE Signal Process. Lett.
Naoya Onizawa, Daisaku Katagiri, Kazumichi Matsumiya, Warren J. Gross, Takahiro Hanyu
2015 — conf
Scaled IIR filter based on stochastic computation.
MWSCAS
Naoya Onizawa, Shunsuke Koshita, Takahiro Hanyu
2015 A conf
Spintronics-based nonvolatile logic-in-memory architecture towards an ultra-low-power and highly reliable VLSI computing paradigm.
DATE
Takahiro Hanyu, Daisuke Suzuki, Naoya Onizawa, Shoun Matsunaga, Masanori Natsui, Akira Mochizuki
2015 — conf
Stochastic implementation of the disparity energy model for depth perception.
SiPS
Kaushik Boga, Naoya Onizawa, François Leduc-Primeau, Kazumichi Matsumiya, Takahiro Hanyu, Warren J. Gross
2015 J jnl
VLSI Implementation of Deep Neural Network Using Integral Stochastic Computing.
CoRR
Arash Ardakani, François Leduc-Primeau, Naoya Onizawa, Takahiro Hanyu, Warren J. Gross
2014 — conf
A Compact Soft-Error Tolerant Asynchronous TCAM Based on a Transistor/Magnetic-Tunnel-Junction Hybrid Dual-Rail Word Structure.
ASYNC
Naoya Onizawa, Shoun Matsunaga, Takahiro Hanyu
2014 J jnl
A Nonvolatile Associative Memory-Based Context-Driven Search Engine Using 90 nm CMOS/MTJ-Hybrid Logic-in-Memory Architecture.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Hooman Jarollahi, Naoya Onizawa, Vincent Gripon, Noboru Sakimura, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu, Warren J. Gross
2014 J jnl
Algorithm and Architecture of Fully-Parallel Associative Memories Based on Sparse Clustered Networks.
J. Signal Process. Syst.
Hooman Jarollahi, Naoya Onizawa, Vincent Gripon, Warren J. Gross
2014 — conf
Algorithm and architecture for a multiple-field context-driven search engine using fully-parallel clustered associative memories.
SiPS
Hooman Jarollahi, Naoya Onizawa, Vincent Gripon, Takahiro Hanyu, Warren J. Gross
2014 — conf
Analog-to-stochastic converter using magnetic-tunnel junction devices.
NANOARCH
Naoya Onizawa, Daisaku Katagiri, Warren J. Gross, Takahiro Hanyu
2014 — conf
Associative Memories Based on Multiple-Valued Sparse Clustered Networks.
ISMVL
Hooman Jarollahi, Naoya Onizawa, Takahiro Hanyu, Warren J. Gross
2014 J jnl
Associative Memories Based on Multiple-Valued Sparse Clustered Networks.
CoRR
Hooman Jarollahi, Naoya Onizawa, Takahiro Hanyu, Warren J. Gross
2014 J jnl
Asynchronous Stochastic Decoding of LDPC Codes: Algorithm and Simulation Model.
IEICE Trans. Inf. Syst.
Naoya Onizawa, Warren J. Gross, Takahiro Hanyu, Vincent C. Gaudet
2014 J jnl
Clockless Stochastic Decoding of Low-Density Parity-Check Codes: Architecture and Simulation Model.
J. Signal Process. Syst.
Naoya Onizawa, Warren J. Gross, Takahiro Hanyu, Vincent C. Gaudet
2014 — conf
Design of a soft-error tolerant 9-transistor/6-magnetic-tunnel-junction hybrid cell based nonvolatile TCAM.
NEWCAS
Naoya Onizawa, Shoun Matsunaga, Takahiro Hanyu
2014 J jnl
High-Throughput Compact Delay-Insensitive Asynchronous NoC Router.
IEEE Trans. Computers
Naoya Onizawa, Atsushi Matsumoto, Tomoyoshi Funazaki, Takahiro Hanyu
2014 J jnl
High-Throughput Low-Energy Self-Timed CAM Based on Reordered Overlapped Search Mechanism.
IEEE Trans. Circuits Syst. I Regul. Pap.
Naoya Onizawa, Shoun Matsunaga, Vincent C. Gaudet, Warren J. Gross, Takahiro Hanyu
2014 J jnl
High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs.
IEICE Trans. Inf. Syst.
Naoya Onizawa, Akira Mochizuki, Hirokatsu Shirahama, Masashi Imai, Tomohiro Yoneda, Takahiro Hanyu
2014 — conf
Highly reliable single-ended current-mode circuit for an inter-chip asynchronous communication link.
APCCAS
Akira Mochizuki, Hirokatsu Shirahama, Naoya Onizawa, Takahiro Hanyu
2014 — conf
Soft-Delay-Error Evaluation in Content-Addressable Memory.
ISMVL
Naoya Onizawa, Shoun Matsunaga, Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Takahiro Hanyu
2014 J jnl
Soft-error tolerant transistor/magnetic-tunnel-junction hybrid non-volatile C-element.
IEICE Electron. Express
Naoya Onizawa, Takahiro Hanyu
2013 — conf
A Low-Energy Variation-Tolerant Asynchronous TCAM for Network Intrusion Detection Systems.
ASYNC
Naoya Onizawa, Warren J. Gross, Takahiro Hanyu
2013 J jnl
A Low-Power Content-Addressable-Memory Based on Clustered-Sparse-Networks
CoRR
Hooman Jarollahi, Vincent Gripon, Naoya Onizawa, Warren J. Gross
2013 — conf
A low-power Content-Addressable Memory based on clustered-sparse networks.
ASAP
Hooman Jarollahi, Vincent Gripon, Naoya Onizawa, Warren J. Gross
2013 J jnl
High-throughput CAM based on a synchronous overlapped search scheme.
IEICE Electron. Express
Naoya Onizawa, Shoun Matsunaga, Vincent C. Gaudet, Warren J. Gross, Takahiro Hanyu
2013 A* conf
Low-power area-efficient large-scale IP lookup engine based on binary-weighted clustered networks.
DAC
Naoya Onizawa, Warren J. Gross
2013 — conf
Lowering Error Floors in Stochastic Decoding of LDPC Codes Based on Wire-Delay Dependent Asynchronous Updating.
ISMVL
Naoya Onizawa, Warren J. Gross, Takahiro Hanyu, Vincent C. Gaudet
2013 J jnl
Open-Fault Resilient Multiple-Valued Codes for Reliable Asynchronous Global Communication Links.
IEICE Trans. Inf. Syst.
Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu
2013 Misc conf
Reduced-complexity binary-weight-coded associative memories.
ICASSP
Hooman Jarollahi, Naoya Onizawa, Vincent Gripon, Warren J. Gross
2013 J jnl
Selective Decoding in Associative Memories Based on Sparse-Clustered Networks.
CoRR
Hooman Jarollahi, Naoya Onizawa, Warren J. Gross
2013 — conf
Selective decoding in associative memories based on Sparse-Clustered Networks.
GlobalSIP
Hooman Jarollahi, Naoya Onizawa, Warren J. Gross
2012 C conf
Architecture and implementation of an associative memory using sparse clustered networks.
ISCAS
Hooman Jarollahi, Naoya Onizawa, Vincent Gripon, Warren J. Gross
2012 — conf
Asynchronous Stochastic Decoding of Low-Density Parity-Check Codes.
ISMVL
Naoya Onizawa, Vincent C. Gaudet, Takahiro Hanyu, Warren J. Gross
2012 — conf
Clockless Stochastic Decoding of Low-Density Parity-Check Codes.
SiPS
Naoya Onizawa, Warren J. Gross, Takahiro Hanyu, Vincent C. Gaudet
2012 — conf
High-Throughput Low-Energy Content-Addressable Memory Based on Self-Timed Overlapped Search Mechanism.
ASYNC
Naoya Onizawa, Shoun Matsunaga, Vincent C. Gaudet, Takahiro Hanyu
2012 J jnl
Long-Range Asynchronous On-Chip Link Based on Multiple-Valued Single-Track Signaling.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu
2012 C conf
Multi-chip NoCs for Automotive Applications.
PRDC
Tomohiro Yoneda, Masashi Imai, Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu
2012 — conf
Systematic Coding Schemes for Low-Power Multiple-Valued Current-Mode Asynchronous Communication Links.
ISMVL
Atsushi Matsumoto, Naoya Onizawa, Takahiro Hanyu
2011 C conf
Adjacent-State monitoring based fine-grained power-gating scheme for a low-power asynchronous pipelined system.
ISCAS
Takao Kawano, Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu
2011 — conf
Complementary Multiple-Valued Encoding Scheme for Interconnect-Fault-Resilient Bidirectional Asynchronous Links.
ISMVL
Atsushi Matsumoto, Naoya Onizawa, Takahiro Hanyu
2011 A conf
Interconnect-fault-resilient delay-insensitive asynchronous communication link based on current-flow monitoring.
DATE
Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu
2011 J jnl
Low-Energy Asynchronous Interleaver for Clockless Fully Parallel LDPC Decoding.
IEEE Trans. Circuits Syst. I Regul. Pap.
Naoya Onizawa, Vincent C. Gaudet, Takahiro Hanyu
2010 — conf
Accurate Asynchronous Network-on-Chip Simulation Based on a Delay-Aware Model.
ISVLSI
Naoya Onizawa, Tomoyoshi Funazaki, Atsushi Matsumoto, Takahiro Hanyu
2010 — conf
Accurate Asynchronous Network-on-Chip Simulation Based on a Delay-Aware Model.
ISVLSI (Selected papers)
Naoya Onizawa, Tomoyoshi Funazaki, Atsushi Matsumoto, Takahiro Hanyu
2010 J jnl
Design of High-Throughput Fully Parallel LDPC Decoders Based on Wire Partitioning.
IEEE Trans. Very Large Scale Integr. Syst.
Naoya Onizawa, Takahiro Hanyu, Vincent C. Gaudet
2010 C conf
High-throughput protocol converter based on an independent encoding/decoding scheme for asynchronous Network-on-Chip.
ISCAS
Naoya Onizawa, Takahiro Hanyu
2010 J jnl
Highly Reliable Multiple-Valued One-Phase Signalling for an Asynchronous On-Chip Communication Link.
IEICE Trans. Inf. Syst.
Naoya Onizawa, Takahiro Hanyu
2010 — conf
One-Color Two-Phase Asynchronous Communication Links Based on Multiple-Valued Simultaneous Control.
ISMVL
Atsushi Matsumoto, Naoya Onizawa, Takahiro Hanyu
2009 J jnl
High-Throughput Bit-Serial LDPC Decoder LSI Based on Multiple-Valued Asynchronous Interleaving.
IEICE Trans. Electron.
Naoya Onizawa, Takahiro Hanyu, Vincent C. Gaudet
2009 C conf
High-performance Asynchronous Intra-chip Communication Link based on a Multiple-valued Current-mode Single-track Scheme.
ISCAS
Yo Ohtake, Naoya Onizawa, Takahiro Hanyu
2009 — conf
Robust Multiple-Valued Current-Mode Circuit Components Based on Adaptive Reference-Voltage Control.
ISMVL
Naoya Onizawa, Takahiro Hanyu
2008 — conf
High-Speed Timing Verification Scheme Using Delay Tables for a Large-Scaled Multiple-Valued Current-Mode Circuit.
ISMVL
Tasuku Nagai, Naoya Onizawa, Takahiro Hanyu
2008 J jnl
Power-Aware Asynchronous Peer-to-Peer Duplex Communication System Based on Multiple-Valued One-Phase Signaling.
IEICE Trans. Electron.
Kazuyasu Mizusawa, Naoya Onizawa, Takahiro Hanyu
2006 J jnl
Design and Evaluation of a NULL-Convention Circuit Based on Dual-Rail Current-Mode Differential Logic.
IEICE Trans. Electron.
Naoya Onizawa, Takahiro Hanyu
2005 — conf
Multiple-Valued Duplex Asynchronous Data Transfer Scheme for Interleaving in LDPC Decoders.
ISMVL
Naoya Onizawa, Akira Mochizuki, Takahiro Hanyu