Naoki Fujieda

28 papers B 2C 1Misc 2Journal 9Unranked 14
YearRankTypeTitle / Venue / Authors
2025 — conf
A flexible FPGA implementation of GNSS signal acquisition circuit using high level synthesis.
CANDARW
Naoki Fujieda, Rei Yokoyama, Takuji Ebinuma
2025 Misc conf
Impact of Optical System Size on Robustness in Laser Speckle Authentication.
MVA
Naoki Fujieda, Kazuya Kitano, Takuya Funatomi, Rui Ishiyama, Yasuhiro Mukaigawa
2024 — conf
A case for edge video processing with FPGA SoC: reversi board detection using Hough transform.
CANDARW
Naoki Fujieda, Naoya Ito
2023 — conf
A Novel Remote FPGA Lab Platform Using MCU-based Controller Board.
TALE
Naoki Fujieda, Atsuki Okuchi
2023 J jnl
Design and Implementation of an On-Line Quality Control System for Latch-Based True Random Number Generator.
IEICE Trans. Inf. Syst.
Naoki Fujieda, Shuichi Ichikawa, Ryusei Oya, Hitomi Kishibe
2022 — conf
An HLS implementation of on-the-fly randomness test for TRNGs.
CANDAR
Ryusei Oya, Naoki Fujieda, Shuichi Ichikawa
2021 — conf
A Python-based evaluation framework for stochastic computing circuits on FPGA SoC.
CANDAR (Workshops)
Naoki Fujieda
2021 J jnl
A true random number generator that utilizes thermal noise in a programmable system-on-chip (PSoC).
Int. J. Circuit Theory Appl.
Shunsuke Matsuoka, Shuichi Ichikawa, Naoki Fujieda
2021 J jnl
An MMCM-based high-speed true random number generator for Xilinx FPGA.
Int. J. Netw. Comput.
Naoki Fujieda, Sogo Takashima
2020 J jnl
An Analysis of DCM-Based True Random Number Generator.
IEEE Trans. Circuits Syst. II Express Briefs
Naoki Fujieda, Masaaki Takeda, Shuichi Ichikawa
2020 — conf
Enhanced use of mixed-mode clock manager for coherent sampling-based true random number generator.
CANDAR (Workshops)
Naoki Fujieda, Sogo Takashima
2020 B conf
On the Feasibility of TERO-Based True Random Number Generator on Xilinx FPGAs.
FPL
Naoki Fujieda
2019 B conf
A light-weight implementation of latch-based true random number generator.
IWCMC
Naoki Fujieda, Hitomi Kishibe, Shuichi Ichikawa
2018 C conf
A Multiple Clock Domain Design of High-radix Montgomery Multiplication for Simplicity.
TENCON
Naoki Fujieda, Yusuke Ayuzawa, Masato Hongo, Shuichi Ichikawa
2018 J jnl
A latch-latch composition of metastability-based true random number generator for Xilinx FPGAs.
IEICE Electron. Express
Naoki Fujieda, Shuichi Ichikawa
2018 — conf
An Analysis on Randomness of Path ORAM for Light-Weight Implementation.
CANDAR Workshops
Hiroki Fujita, Naoki Fujieda, Shuichi Ichikawa
2018 J jnl
Evaluation of Register Number Abstraction for Enhanced Instruction Register Files.
IEICE Trans. Inf. Syst.
Naoki Fujieda, Kiyohiro Sato, Ryodai Iwamoto, Shuichi Ichikawa
2017 J jnl
A Virtual Cache for Overlapped Memory Accesses of Path ORAM.
Int. J. Netw. Comput.
Naoki Fujieda, Ryo Yamauchi, Hiroki Fujita, Shuichi Ichikawa
2017 — conf
An Obfuscated Hardwired Sequence Control System Generated by High Level Synthesis.
CANDAR
Yoshiki Ishigaki, Naoki Fujieda, Yuumi Matsuoka, Kazuki Uyama, Shuichi Ichikawa
2017 — conf
Evaluation of the hardwired sequence control system generated by high-level synthesis.
ISIE
Naoki Fujieda, Shuichi Ichikawa, Yoshiki Ishigaki, Tasuku Tanaka
2016 J jnl
Design and implementation of instruction indirection for embedded software obfuscation.
Microprocess. Microsystems
Naoki Fujieda, Tasuku Tanaka, Shuichi Ichikawa
2016 — conf
Last Path Caching: A Simple Way to Remove Redundant Memory Accesses of Path ORAM.
CANDAR
Naoki Fujieda, Ryo Yamauchi, Shuichi Ichikawa
2015 — conf
A Complement to Enhanced Instruction Register File against Embedded Software Falsification.
PPREW@ACSAC
Naoki Fujieda, Kiyohiro Sato, Shuichi Ichikawa
2013 — conf
An XOR-Based Approach to Merging Entries for Instruction Register Files.
CANDAR
Naoki Fujieda, Shuichi Ichikawa
2012 — conf
ScalableCore System: A Scalable Many-Core Simulator by Employing over 100 FPGAs.
ARC
Shinya Takamaeda-Yamazaki, Shintaro Sano, Yoshito Sakaguchi, Naoki Fujieda, Kenji Kise
2011 Misc conf
A Partitioning Method of Cooperative Caching with Hit Frequency Counters for Many-Core Processors.
ICNC
Naoki Fujieda, Kenji Kise
2011 — conf
Rethinking processor instruction fetch: Inefficiencies-cracking mechanism.
ISOCC
Mochamad Asri, Naoki Fujieda, Kenji Kise
2009 J jnl
SimCell: A Processor Simulator for Multi-Core Architecture Research.
Inf. Media Technol.
Shimpei Sato, Naoki Fujieda, Akira Moriya, Kenji Kise