Naofumi Takagi

92 papers A 1C 14Misc 1Journal 64Unranked 9
YearRankTypeTitle / Venue / Authors
2022 J jnl
32-Bit ALU with Clockless Gates for RSFQ Bit-Parallel Processor.
IEICE Trans. Electron.
Takahiro Kawaguchi, Naofumi Takagi
2021 — conf
Zytlebot : FPGA integrated ros-based autonomous mobile robot.
FPT
Ryota Miyagi, Naofumi Takagi, Sho Kinoshista, Masashi Oda, Hideki Takase
2020 J jnl
mROS: A Lightweight Runtime Environment of ROS 1 nodes for Embedded Devices.
J. Inf. Process.
Hideki Takase, Tomoya Mori, Kazuyoshi Takagi, Naofumi Takagi
2019 C ed.
26th IEEE Symposium on Computer Arithmetic, ARITH 2019, Kyoto, Japan, June 10-12, 2019
ARITH
Naofumi Takagi, Sylvie Boldo, Martin Langhammer
2019 J jnl
Concurrent Error Detectable Carry Select Adder with Easy Testability.
IEEE Trans. Computers
Nobutaka Kito, Naofumi Takagi
2019 J jnl
Conversion of Logic Gates in Netlists for Rapid Single Flux Quantum Circuits Utilizing Confluence of Pulses.
IPSJ Trans. Syst. LSI Des. Methodol.
Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi
2019 — conf
mROS: A Lightweight Runtime Environment for Robot Software Components onto Embedded Devices.
HEART
Hideki Takase, Tomoya Mori, Kazuyoshi Takagi, Naofumi Takagi
2018 J jnl
Algorithms for Evaluating the Matrix Polynomial
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Kotaro Matsumoto, Kazuyoshi Takagi, Naofumi Takagi
2018 Misc conf
Design concept of a lightweight runtime environment for robot software components onto embedded devices: work-in-progress.
EMSOFT
Hideki Takase, Tomoya Mori, Kazuyoshi Takagi, Naofumi Takagi
2017 J jnl
Floating-Point Multiplier with Concurrent Error Detection Capability by Partial Duplication.
IEICE Trans. Inf. Syst.
Nobutaka Kito, Kazushi Akimoto, Naofumi Takagi
2017 J jnl
Recap of the 22nd Asia and South- Pacific Design Automation Conference.
IEEE Des. Test
Naofumi Takagi
2016 — conf
An evaluation framework of OS-level power managements for the big.LITTLE architecture.
NEWCAS
Hideki Takase, Kazumi Aono, Yutaka Matsubara, Kazuyoshi Takagi, Naofumi Takagi
2016 J jnl
High-Throughput Rapid Single-Flux-Quantum Circuit Implementations for Exponential and Logarithm Computation Using the Radix-2 Signed-Digit Representation.
IEICE Trans. Electron.
Masamitsu Tanaka, Kazuyoshi Takagi, Naofumi Takagi
2016 J jnl
RSFQ 4-bit Bit-Slice Integer Multiplier.
IEICE Trans. Electron.
Guang-Ming Tang, Kazuyoshi Takagi, Naofumi Takagi
2015 J jnl
A Verification Method for Single-Flux-Quantum Circuits Using Delay-Based Time Frame Model.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Takahiro Kawaguchi, Kazuyoshi Takagi, Naofumi Takagi
2015 J jnl
An Allocation Optimization Method for Partially-reliable Scratch-pad Memory in Embedded Systems.
Inf. Media Technol.
Takuya Hatayama, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi
2015 J jnl
An Allocation Optimization Method for Partially-reliable Scratch-pad Memory in Embedded Systems.
IPSJ Trans. Syst. LSI Des. Methodol.
Takuya Hatayama, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi
2014 J jnl
A Reconfigurable Data-Path Accelerator Based on Single Flux Quantum Circuits.
IEICE Trans. Electron.
Hiroshi Kataoka, Hiroaki Honda, Farhad Mehdipour, Nobuyuki Yoshikawa, Akira Fujimaki, Hiroyuki Akaike, Naofumi Takagi, Kazuaki J. Murakami
2014 — conf
An Operation Scenario Model for Energy Harvesting Embedded Systems and an Algorithm to Maximize the Operation Quality.
HPCC/CSS/ICESS
Kazumi Aono, Atsushi Iwata, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi
2014 J jnl
Circuit Description and Design Flow of Superconducting SFQ Logic Circuits.
IEICE Trans. Electron.
Kazuyoshi Takagi, Nobutaka Kito, Naofumi Takagi
2014 J jnl
Design and High-Speed Demonstration of Single-Flux-Quantum Bit-Serial Floating-Point Multipliers Using a 10kA/cm
IEICE Trans. Electron.
Xizhu Peng, Yuki Yamanashi, Nobuyuki Yoshikawa, Akira Fujimaki, Naofumi Takagi, Kazuyoshi Takagi, Mutsuo Hidaka
2014 J jnl
Large-Scale Integrated Circuit Design Based on a Nb Nine-Layer Structure for Reconfigurable Data-Path Processors.
IEICE Trans. Electron.
Akira Fujimaki, Masamitsu Tanaka, Ryo Kasagi, Katsumi Takagi, Masakazu Okada, Yuhi Hayakawa, Kensuke Takata, Hiroyuki Akaike, Nobuyuki Yoshikawa, Shuichi Nagasawa, Kazuyoshi Takagi, Naofumi Takagi
2014 J jnl
Nb 9-Layer Fabrication Process for Superconducting Large-Scale SFQ Circuits and Its Process Evaluation.
IEICE Trans. Electron.
Shuichi Nagasawa, Kenji Hinode, Tetsuro Satoh, Mutsuo Hidaka, Hiroyuki Akaike, Akira Fujimaki, Nobuyuki Yoshikawa, Kazuyoshi Takagi, Naofumi Takagi
2014 J jnl
Nested Loop Parallelization Using Polyhedral Optimization in High-Level Synthesis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Akihiro Suda, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi
2013 — conf
A Buffering Method for Parallelized Loop with Non-Uniform Dependencies in High-Level Synthesis.
ICA3PP (1)
Akihiro Suda, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi
2013 J jnl
Low-Overhead Fault-Secure Parallel Prefix Adder by Carry-Bit Duplication.
IEICE Trans. Inf. Syst.
Nobutaka Kito, Naofumi Takagi
2012 J jnl
A C-Testable Multiple-Block Carry Select Adder.
IEICE Trans. Inf. Syst.
Nobutaka Kito, Shinichi Fujii, Naofumi Takagi
2012 J jnl
A VLSI Architecture with Multiple Fast Store-Based Block Parallel Processing for Output Probability and Likelihood Score Computations in HMM-Based Isolated Word Recognition.
IEICE Trans. Electron.
Kazuhiro Nakamura, Ryo Shimazaki, Masatoshi Yamamoto, Kazuyoshi Takagi, Naofumi Takagi
2012 J jnl
Fast inversion algorithm in GF(2
IET Comput. Digit. Tech.
Katsuki Kobayashi, Naofumi Takagi, Kazuyoshi Takagi
2011 J jnl
Layout-Driven Skewed Clock Tree Synthesis for Superconducting SFQ Circuits.
IEICE Trans. Electron.
Kazuyoshi Takagi, Yuki Ito, Shota Takeshima, Masamitsu Tanaka, Naofumi Takagi
2011 J jnl
Partial Product Generation Utilizing the Sum of Operands for Reduced Area Parallel Multipliers.
Inf. Media Technol.
Hirotaka Kawashima, Naofumi Takagi
2011 J jnl
Partial Product Generation Utilizing the Sum of Operands for Reduced Area Parallel Multipliers.
IPSJ Trans. Syst. LSI Des. Methodol.
Hirotaka Kawashima, Naofumi Takagi
2010 J jnl
100 GHz Demonstrations Based on the Single-Flux-Quantum Cell Library for the 10 kA/cm
IEICE Trans. Electron.
Yuki Yamanashi, Toshiki Kainuma, Nobuyuki Yoshikawa, Irina Kataeva, Hiroyuki Akaike, Akira Fujimaki, Masamitsu Tanaka, Naofumi Takagi, Shuichi Nagasawa, Mutsuo Hidaka
2010 J jnl
A C-Testable 4-2 Adder Tree for an Easily Testable High-Speed Multiplier.
IEICE Trans. Inf. Syst.
Nobutaka Kito, Kensuke Hanai, Naofumi Takagi
2010 J jnl
A VLSI Architecture for Output Probability Computations of HMM-Based Recognition Systems with Store-Based Block Parallel Processing.
IEICE Trans. Inf. Syst.
Kazuhiro Nakamura, Masatoshi Yamamoto, Kazuyoshi Takagi, Naofumi Takagi
2010 J jnl
Automated Passive-Transmission-Line Routing Tool for Single-Flux-Quantum Circuits Based on A* Algorithm.
IEICE Trans. Electron.
Masamitsu Tanaka, Koji Obata, Yuki Ito, Shota Takeshima, Motoki Sato, Kazuyoshi Takagi, Naofumi Takagi, Hiroyuki Akaike, Akira Fujimaki
2010 J jnl
Comparisons of Synchronous-Clocking SFQ Adders.
IEICE Trans. Electron.
Naofumi Takagi, Masamitsu Tanaka
2009 J jnl
Fast Hardware Algorithm for Division in hbox 2
IEEE Trans. Circuits Syst. II Express Briefs
Katsuki Kobayashi, Naofumi Takagi
2008 J jnl
A Clock Scheduling Algorithm for High-Throughput RSFQ Digital Circuits.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Koji Obata, Kazuyoshi Takagi, Naofumi Takagi
2008 J jnl
A Combined Circuit for Multiplication and Inversion in GF(2
IEEE Trans. Circuits Syst. II Express Briefs
Katsuki Kobayashi, Naofumi Takagi
2008 J jnl
Bipartite Modular Multiplication Method.
IEEE Trans. Computers
Marcelo E. Kaihara, Naofumi Takagi
2008 C conf
Fast and memory efficient VLSI architecture for output probability computations of HMM-based recognition systems.
ISCAS
Kazuhiro Nakamura, Masatoshi Yamamoto, Kazuyoshi Takagi, Naofumi Takagi
2008 — conf
Level-Testability of Multi-operand Adders.
ATS
Nobutaka Kito, Naofumi Takagi
2008 J jnl
Proposal of a Desk-Side Supercomputer with Reconfigurable Data-Paths Using Rapid Single-Flux-Quantum Circuits.
IEICE Trans. Electron.
Naofumi Takagi, Kazuaki J. Murakami, Akira Fujimaki, Nobuyuki Yoshikawa, Koji Inoue, Hiroaki Honda
2007 J jnl
A Method of Sequential Circuit Synthesis Using One-Hot Encoding for Single-Flux-Quantum Digital Circuits.
IEICE Trans. Electron.
Koji Obata, Kazuyoshi Takagi, Naofumi Takagi
2007 C conf
An Algorithm for Inversion in GF(2^m) Suitable for Implementation Using a Polynomial Multiply Instruction on GF(2).
IEEE Symposium on Computer Arithmetic
Katsuki Kobayashi, Naofumi Takagi, Kazuyoshi Takagi
2007 J jnl
Logic Synthesis Method for Dual-Rail RSFQ Digital Circuits Using Root-Shared Binary Decision Diagrams.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Koji Obata, Kazuyoshi Takagi, Naofumi Takagi
2006 J jnl
A Hardware Algorithm for Integer Division Using the SD2 Representation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Naofumi Takagi, Shunsuke Kadowaki, Kazuyoshi Takagi
2006 J jnl
Hardware Algorithm for Computing Reciprocal of Euclidean Norm of a 3-D Vector.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Fumio Kumazawa, Naofumi Takagi
2005 C conf
A Hardware Algorithm for Integer Division.
IEEE Symposium on Computer Arithmetic
Naofumi Takagi, Shunsuke Kadowaki, Kazuyoshi Takagi
2005 J jnl
A Hardware Algorithm for Modular Multiplication/Division Based on the Extended Euclidean Algorithm.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Marcelo E. Kaihara, Naofumi Takagi
2005 J jnl
A Hardware Algorithm for Modular Multiplication/Division.
IEEE Trans. Computers
Marcelo E. Kaihara, Naofumi Takagi
2005 A conf
Bipartite Modular Multiplication.
CHES
Marcelo E. Kaihara, Naofumi Takagi
2004 J jnl
Systematic IEEE rounding method for high-speed floating-point multipliers.
IEEE Trans. Very Large Scale Integr. Syst.
Nhon T. Quach, Naofumi Takagi, Michael J. Flynn
2003 C conf
A VLSI Algorithm for Modular Multiplication/Division.
IEEE Symposium on Computer Arithmetic
Marcelo E. Kaihara, Naofumi Takagi
2003 J jnl
Digit-Recurrence Algorithm for Computing Reciprocal Square-Root.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Naofumi Takagi, Daisuke Matsuoka, Kazuyoshi Takagi
2002 J jnl
A VLSI Algorithm for Division in GF(2
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yasuaki Watanabe, Naofumi Takagi, Kazuyoshi Takagi
2002 — conf
Multiple-Valued-Digit Number Representations in Arithmetic Circuit Algorithms.
ISMVL
Naofumi Takagi
2002 — conf
Special Session: Security on SoC.
ISSS
Hiroto Yasuura, Naofumi Takagi, Srivaths Ravi, Michael Torla, Catherine H. Gebotys
2001 J jnl
A Fast Algorithm for Multiplicative Inversion in GF(2m) Using Normal Basis.
IEEE Trans. Computers
Naofumi Takagi, Jun-ichi Yoshiki, Kazuyoshi Takagi
2001 C conf
A Hardware Algorithm for Computing Reciprocal Square Root.
IEEE Symposium on Computer Arithmetic
Naofumi Takagi
2000 J jnl
A VLSI Algorithm for Computing the Euclidean Norm of a 3D Vector.
IEEE Trans. Computers
Naofumi Takagi, Seiji Kuwahara
2000 J jnl
A fast addition algorithm for elliptic curve arithmetic in GF(2
Inf. Process. Lett.
Akira Higuchi, Naofumi Takagi
1999 J jnl
A High-Speed Reduced-Size Adder Under Left-to-Right Input Arrival.
IEEE Trans. Computers
Naofumi Takagi, Takashi Horiyama
1999 — ch.
Adders.
The VLSI Handbook
Naofumi Takagi, Haruyuki Tago, Charles R. Baugh, Saburo Muroga
1999 C conf
Digit-Recurrence Algorithm for Computing Euclidean Norm of a 3-D Vector.
IEEE Symposium on Computer Arithmetic
Naofumi Takagi, Seiji Kuwahara
1999 — ch.
Dividers.
The VLSI Handbook
Naofumi Takagi, Saburo Muroga
1999 — ch.
Multipliers.
The VLSI Handbook
Naofumi Takagi, Charles R. Baugh, Saburo Muroga
1998 J jnl
Powering by a Table Look-Up and a Multiplication with Operand Modification.
IEEE Trans. Computers
Naofumi Takagi
1997 J jnl
Efficient Initial Approximation for Multiplicative Division and Square Root by a Multiplication with Operand Modification.
IEEE Trans. Computers
Masayuki Ito, Naofumi Takagi, Shuzo Yajima
1997 C conf
Generating a Power of an Operand by a Table Look-up and a Multiplication.
IEEE Symposium on Computer Arithmetic
Naofumi Takagi
1997 J jnl
O(n)-Depth Modular Exponentiation Circuit Algorithm.
IEEE Trans. Computers
Takafumi Hamano, Naofumi Takagi, Shuzo Yajima, Franco P. Preparata
1996 J jnl
Square Rooting by Iterative Multiply-Additions.
Inf. Process. Lett.
Masayuki Ito, Naofumi Takagi, Shuzo Yajima
1995 J jnl
A Multiple-Precision Modular Multiplication Algorithm with Triangle Additions.
IEICE Trans. Inf. Syst.
Naofumi Takagi
1995 C conf
Efficient Initial Approximation and Fast Converging Methods for Division and Square Root.
IEEE Symposium on Computer Arithmetic
Masayuki Ito, Naofumi Takagi, Shuzo Yajima
1995 C conf
Function Evaluation by Table Look-up and Addition.
IEEE Symposium on Computer Arithmetic
Hannes Hassler, Naofumi Takagi
1995 C conf
O(n)-depth circuit algorithm for modular exponentiation.
IEEE Symposium on Computer Arithmetic
Takafumi Hamano, Naofumi Takagi, Shuzo Yajima, Franco P. Preparata
1993 C conf
A modular multiplication algorithm with triangle additions.
IEEE Symposium on Computer Arithmetic
Naofumi Takagi
1992 J jnl
A Radix-4 Modular Multiplication Hardware Algorithm for Modular Exponentiation.
IEEE Trans. Computers
Naofumi Takagi
1992 J jnl
Modular Multiplication Hardware Algorithms with a Redundant Representation and Their Application to RSA Cryptosystem.
IEEE Trans. Computers
Naofumi Takagi, Shuzo Yajima
1991 C conf
A radix-4 modular multiplication hardware algorithm efficient for iterative modular multiplications.
IEEE Symposium on Computer Arithmetic
Naofumi Takagi
1991 J jnl
An on-line error-detectable high-speed array divider.
Syst. Comput. Jpn.
Naofumi Takagi, Shuzo Yajima
1991 J jnl
Redundant CORDIC Methods with a Constant Scale Factor for Sine and Cosine Computation.
IEEE Trans. Computers
Naofumi Takagi, Tohru Asada, Shuzo Yajima
1988 — conf
An on-line error-detectable array divider with a redundant binary representation and a residue code.
FTCS
Naofumi Takagi, Shuzo Yajima
1987 J jnl
A hardware algorithm for computing sine and cosine using redundant binary representation.
Syst. Comput. Jpn.
Naofumi Takagi, Tohru Asada, Shuzo Yajima
1987 C conf
Design of high speed MOS multiplier and divider using redundant binary representation.
IEEE Symposium on Computer Arithmetic
Shigeo Kuninobu, Tamotsu Nishiyama, Hisakazu Edamatsu, Takashi Taniguchi, Naofumi Takagi
1987 J jnl
On high-speed parallel algorithms using redundant coding.
Syst. Comput. Jpn.
Hiroto Yasuura, Naofumi Takagi, Shuzo Yajima
1987 J jnl
On-Line Error-Detectable High-Speed Multiplier Using Redundant Binary Representation and Three-Rail Logic.
IEEE Trans. Computers
Naofumi Takagi, Shuzo Yajima
1986 J jnl
A square root hardware algorithm using redundant binary representation.
Syst. Comput. Jpn.
Naofumi Takagi, Shuzo Yajima
1986 J jnl
Hardware algorithms for computing exponentials and logarithms using redundant binary representation.
Syst. Comput. Jpn.
Naofumi Takagi, Shuzo Yajima
1985 J jnl
High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree.
IEEE Trans. Computers
Naofumi Takagi, Hiroto Yasuura, Shuzo Yajima
1982 J jnl
The Parallel Enumeration Sorting Scheme for VLSI.
IEEE Trans. Computers
Hiroto Yasuura, Naofumi Takagi, Shuzo Yajima