Nanjian Wu - RankMe

136 papers C 7Journal 61Unranked 68

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	8.5 A 112Gb/s 0.76pJ/b Reference-Less Mixed-Signal PAM-4 CDR in 28nm CMOS. ISSCC Zhaoyu Zhang, Yiqing Xu, Jian Liu, Nanjian Wu, Zhao Zhang, Liyuan Liu
2026	—	`conf`	A 0.65-to-1V-VDD 10.5-to-11.85GHz Fractional-N Sampling PLL Achieving 71.47fs Integrated Jitter and <-60dBc Near-Integer Fractional Spur in 40nm CMOS. ISSCC Yixi Li, Junjie Chen, Xinyu Shen, Jie Yang, Jian Liu, Nanjian Wu, Zhao Zhang, Liyuan Liu
2026	J	`jnl`	A 10 000-Inference/s Bio-Inspired Spiking Vision Chip Based on an End-to-End SNN Embedding Image Signal Enhancement. IEEE J. Solid State Circuits Xu Yang, Fuming Lei, Na Tian, Cong Shi, Zhe Wang, Shuangming Yu, Runjiang Dou, Peng Feng, Nan Qi, Zhongming Wei, Jian Liu, Kaiyou Wang, Nanjian Wu, Liyuan Liu
2025	—	`conf`	19.8 A 0.65V-VDD 10.4-to-11.8GHz Fractional-N Sampling PLL Achieving 73.8fsrms Jitter, -271.5dB FoMN, and -61 dBc in-Band Fractional Spur in 40nm CMOS. ISSCC Xinyu Shen, Zhao Zhang, Yixi Li, Junjie Chen, Xiangjian Kong, Nan Qi, Jian Liu, Nanjian Wu, Liyuan Liu
2025	J	`jnl`	A 0.006-mm IEEE Trans. Circuits Syst. II Express Briefs Yixi Li, Zhao Zhang, Xinyu Shen, Jian Liu, Nanjian Wu, Liyuan Liu
2025	J	`jnl`	A 56-Gb/s 0.11-pJ/bit/dB energy-efficient PAM-4 transmitter using push-pull current-mode driver and DDJ-suppressed multiplexer. IEICE Electron. Express Zhaoyu Zhang, Yadong Xiao, Jian Liu, Nanjian Wu, Zhao Zhang, Liyuan Liu
2025	J	`jnl`	A 56-Gb/s, 6.3-pJ/bit PAM-4 DFB Laser Driver Incorporating Asymmetric Equalization and Integrated CDR in 28 nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. Yang Min, Nan Qi, Yihan Chen, Yi Zhang, Minye Zhu, Guike Li, Yonghui Lin, Huiyao Peng, Mo Guang, Kaiwen Long, Zhao Zhang, Jian Liu, Nanjian Wu, Jingbo Shi, Yong Chen, Frank F. Shi, Liyuan Liu
2025	J	`jnl`	A 75.6 Gb/s 22-bit Floating-Point Coarse-Grained Versatile DSP Embedding 26K-Point Baseband Signal Processing and 2048 × 256-Point Complex FFT. IEEE Trans. Circuits Syst. I Regul. Pap. Xuanzhe Xu, Xianjun Liu, Siyuan Wei, Shuangming Yu, Runjiang Dou, Xu Yang, Zhe Wang, Jian Liu, Nanjian Wu, Liyuan Liu
2024	—	`conf`	A 0.144 mm CICC Xinyu Shen, Zhao Zhang, Yong Chen, Yixi Li, Yidan Zhang, Guike Li, Nan Qi, Jian Liu, Nanjian Wu, Liyuan Liu
2024	—	`conf`	A 13.75-14.75-GHz 32.1-fsRMS Jitter -100.6-dBc Reference Spur -261.4-dB FoM Sub-Sampling PLL Using a KPD-Doubled Isolated Sub-Sampling Phase Detector for Reliable Spur-Jitter-Joint Optimization. A-SSCC Yiqing Xu, Yixi Li, Zhao Zhang, Nan Qi, Jian Liu, Nanjian Wu, Liyuan Liu
2024	J	`jnl`	A 3 THz CMOS Image Sensor. IEEE J. Solid State Circuits Min Liu, Ziteng Cai, Zhe Wang, Shaohua Zhou, Man-Kay Law, Jian Liu, Jianguo Ma, Nanjian Wu, Liyuan Liu
2024	C	`conf`	A 32Gb/s NRZ Low-Bias DFB Driver with Frequency Boosting for High Efficiency Data Transmission. ISCAS Yang Min, Yi Zhang, Tao Yang, Leliang Li, Guike Li, Zhao Zhang, Jian Liu, Nanjian Wu, Yonghui Lin, Huiyao Peng, Jingbo Shi, Nan Qi
2024	—	`conf`	A 3μm Pixel Device for Peak Power Mitigation of Global-Shutter Indirect Time of Flight Image Sensor. ICTA Ruotong Yin, Yinlei Liang, Weizhe Zhang, Peng Feng, Zhe Wang, Runjiang Dou, Jian Liu, Nanjian Wu, Liyuan Liu
2024	J	`jnl`	A 64 × 128 3D-Stacked SPAD Image Sensor for Low-Light Imaging. Sensors Zhe Wang, Xu Yang, Na Tian, Min Liu, Ziteng Cai, Peng Feng, Runjiang Dou, Shuangming Yu, Nanjian Wu, Jian Liu, Liyuan Liu
2024	—	`conf`	A 64Gb/s Si-Photonic Micro-Ring Resonator Transceiver with Co-designed CMOS Driver and TIA for WDM Optical-IO. BCICTS Qianli Ma, Sikai Chen, Jintao Xue, Yingjie Ma, Yuean Gu, Chao Cheng, Yihan Chen, Haoran Yin, Guike Li, Zhao Zhang, Nanjian Wu, Ke Li, Lei Wang, Ming Li, Chao Xiang, Binhao Wang, Nan Qi, Liyuan Liu
2024	—	`conf`	A 75.6Gb/S 22-Bit Floating-Point Reconfigurable DSP Accelerator Embedding 2048×256-Point Complex FFT and 26K-Point 1-D Signal Processing. A-SSCC Xuanzhe Xu, Xianjun Liu, Siyuan Wei, Shuangming Yu, Runjiang Dou, Xu Yang, Zhe Wang, Jian Liu, Nanjian Wu, Liyuan Liu
2024	J	`jnl`	A Bio-Inspired Spiking Vision Chip Based on SPAD Imaging and Direct Spike Computing for Versatile Edge Vision. IEEE J. Solid State Circuits Xu Yang, Chunhe Yao, Lei Kang, Qian Luo, Nan Qi, Runjiang Dou, Shuangming Yu, Peng Feng, Zhongming Wei, Jian Liu, Kaiyou Wang, Nanjian Wu, Liyuan Liu
2024	J	`jnl`	A Real-Time 2D/3D Perception Visual Vector Processor for 1920 × 1080 High-Resolution High-Speed Intelligent Vision Chips. IEEE Trans. Circuits Syst. I Regul. Pap. Siyuan Wei, Ke Ning, Lei Kang, Xuemin Zheng, Mingxin Zhao, Mengmeng Xu, Shuyu Wang, Xuanzhe Xu, Runjiang Dou, Shuangming Yu, Xu Yang, Jian Liu, Cong Shi, Nanjian Wu, Liyuan Liu
2024	J	`jnl`	A visual cortex-inspired edge neuromorphic hardware architecture with on-chip multi-layer STDP learning. Comput. Electr. Eng. Junxian He, Min Tian, Ying Jiang, Haibing Wang, Tengxiao Wang, Xichuan Zhou, Liyuan Liu, Nanjian Wu, Ying Wang, Cong Shi
2024	J	`jnl`	DT-SCNN: dual-threshold spiking convolutional neural network with fewer operations and memory access for edge applications. Frontiers Comput. Neurosci. Fuming Lei, Xu Yang, Jian Liu, Runjiang Dou, Nanjian Wu
2024	—	`conf`	Edge-type High-speed Intelligent Infrared Pre-processor. ICTA Yuxiao Wen, Runjiang Dou, Yongchao Deng, Chi Zhang, Huanhui Zhang, Shuangming Yu, Jian Liu, Nanjian Wu, Liyuan Liu
2024	J	`jnl`	Ghost Reservoir: A Memory-Efficient Low-Power and Real-Time Neuromorphic Processor of Liquid State Machine With On-Chip Learning. IEEE Trans. Circuits Syst. II Express Briefs Cong Shi, Xiang Fu, Haibing Wang, Yingcheng Lin, Ying Jiang, Liyuan Liu, Nanjian Wu, Min Tian
2024	—	`conf`	Invited Paper: Area Efficient Low Power Data Transmission Circuit with Analog Differential Data Selector for CMOS Image Sensor. ICTA Fangqiang Zhan, Weizhe Zhang, Peng Feng, Runjiang Dou, Jian Liu, Nanjian Wu, Liyuan Liu
2023	—	`conf`	A $\boldsymbol{4} \times \boldsymbol{112}-\mathbf{Gb}/\mathbf{s}$ PAM-4 Silicon-Photonic Transceiver Front-End for Linear-Drive Co-Packaged Optics. A-SSCC Han Liu, Nan Qi, Donglai Lu, Zizheng Dong, Zhihan Zhang, Jian He, Guike Li, Leliang Li, Ye Liu, Ziyue Dang, Daigao Chen, Zhao Zhang, Jian Liu, Nanjian Wu, Xi Xiao, Liyuan Liu
2023	—	`conf`	A 0.0035-mm ESSCIRC Zhaoyu Zhang, Zhao Zhang, Yong Chen, Guoqing Wang, Xinyu Shen, Nan Qi, Guike Li, Shuangming Yu, Jian Liu, Nanjian Wu, Liyuan Liu
2023	—	`conf`	A 12.75-to-16-GHz Spur-Jitter-Joint-Optimization SS-PLL Achieving -94.55-dBc Reference Spur, 31.9-fs Integrated Jitter and -260.1-dB FoM. A-SSCC Yixi Li, Zhao Zhang, Yong Chen, Xinyu Shen, Nan Qi, Jian Liu, Nanjian Wu, Liyuan Liu
2023	—	`conf`	A 128×128 15µm-Pitch DROIC with Pixel-Level 14-Bit ADC. ICTA Huanhui Zhang, Xu Yang, Zhe Wang, Shuangming Yu, Peng Feng, Jian Liu, Nanjian Wu, Runjiang Dou, Liyuan Liu
2023	—	`conf`	A 16.4kPixel 3.08-to-3.86THz Digital Real-Time CMOS Image Sensor with 73dB Dynamic Range. ISSCC Min Liu, Ziteng Cai, Shaohua Zhou, Man-Kay Law, Jian Liu, Jianguo Ma, Nanjian Wu, Liyuan Liu
2023	J	`jnl`	A 24.3 μJ/Image SNN Accelerator for DVS-Gesture With WS-LOS Dataflow and Sparse Methods. IEEE Trans. Circuits Syst. II Express Briefs Lei Kang, Xu Yang, Chi Zhang, Shuangming Yu, Runjiang Dou, Wenchang Li, Cong Shi, Jian Liu, Nanjian Wu, Liyuan Liu
2023	—	`conf`	A 4-12.1-GHz Fractional-N Ring Sampling PLL Based on Adaptively-Biased PD-Merged DTC Achieving -37.6± 0.9-dBc Integrated Phase Noise, 261.9-fs RMS Jitter, and -240.6-dB FoM. ESSCIRC Xinyu Shen, Zhao Zhang, Guike Li, Yong Chen, Nan Qi, Jian Liu, Nanjian Wu, Liyuan Liu
2023	J	`jnl`	A 50Gb/s CMOS Optical Receiver With Si-Photonics PD for High-Speed Low-Latency Chiplet I/O. IEEE Trans. Circuits Syst. I Regul. Pap. Sikai Chen, Mingyang You, Yunqi Yang, Ye Jin, Ziyi Lin, Yihong Li, Leliang Li, Guike Li, Yujun Xie, Zhao Zhang, Binhao Wang, Ningfeng Tang, Faju Liu, Zheyu Fang, Jian Liu, Nanjian Wu, Yong Chen, Liyuan Liu, Ninghua Zhu, Ming Li, Nan Qi
2023	—	`conf`	A 64-Gb/s 0.33-pJ/bit PAM4 Receiver Analog Front-End with a Single-Stage Triple-Peaking CTLE Achieving 22.5-dB Boost in 40-nm CMOS Process. ICTA Guoqing Wang, Zhao Zhang, Xinyu Shen, Zhaoyu Zhang, Jian Liu, Nanjian Wu, Liyuan Liu
2023	—	`conf`	A 64-Gb/s Reference-Less PAM4 CDR with Asymmetrical Linear Phase Detector Soring 231.5-fsrms Clock Jitter and 0.21-pJ/bit Energy Efficiency in 40-nm CMOS. VLSI Technology and Circuits Zhao Zhang, Zhaoyu Zhang, Yong Chen, Nan Qi, Jian Liu, Nanjian Wu, Liyuan Liu
2023	—	`conf`	A Lightweight Integer-STBP On-Chip Learning Method of Spiking Neural Networks For Edge Processors. ICTA Fuming Lei, Xu Yang, Jian Liu, Nanjian Wu, Cong Shi, Runjiang Dou, Liyuan Liu
2023	—	`conf`	A O.4V-VDD 2.25-to-2.75GHz ULV-SS-PLL Achieving 236.6fsrms Jitter, -253.8dB Jitter-Power FoM, and -76.1dBc Reference Spur. ISSCC Zhao Zhang, Xinyu Shen, Zhaoyu Zhang, Guike Li, Nan Qi, Jian Liu, Yong Chen, Nanjian Wu, Liyuan Liu
2023	—	`conf`	A Wideband Low-Noise Linear LiDAR Analog Front-End Achieving 1.6 GHz Bandwidth, $\boldsymbol{2.7}\ \mathbf{pA}/\mathbf{Hz}^{\boldsymbol{0.5}}$ Input Referred Noise, and 103 $\mathbf{dB}\mathbf{\Omega}$ Transimpedance Gain. A-SSCC Yidan Zhang, Zhao Zhang, Yiqing Xu, Xinyu Shen, Nan Qi, Nanjian Wu, Jian Liu, Liyuan Liu
2023	J	`jnl`	An 8-T Processing-in-Memory SRAM Cell-Based Pixel-Parallel Array Processor for Vision Chips. IEEE Trans. Circuits Syst. I Regul. Pap. Leyi Chen, Cong Shi, Junxian He, Jianyi Yu, Haibing Wang, Jing Lu, Liyuan Liu, Nanjian Wu, Min Tian
2023	C	`conf`	An 800G Integrated Silicon-Photonic Transmitter based on 16-Channel Mach-Zehnder Modulator and Co-Designed 5.35pJ/bit CMOS Drivers. ISCAS Jingbo Shi, Han Liu, Tao Yang, Ming Jin, Haowen Shu, Fenghe Yang, Lei Shi, Yuansheng Tao, Jianrui Deng, Ruixuan Chen, Changhao Han, Jian Liu, Nanjian Wu, Nan Qi, Liyuan Liu
2023	J	`jnl`	Hierarchical Parallel Vision Processor for High-Speed Ship Detection. IEEE Trans. Circuits Syst. II Express Briefs Mengmeng Xu, Zhongxing Zhang, Honglong Li, Qian Luo, Runjiang Dou, Liyuan Liu, Jian Liu, Nanjian Wu
2023	—	`conf`	Live Demonstration: Face Recognition at The Edge Using Fast On-Chip Deep Learning Neuromorphic Chip. AICAS Zhengqing Zhong, Tengxiao Wang, Haibing Wang, Zhihua Zhou, Junxian He, Fang Tang, Xichuan Zhou, Shuangming Yu, Liyuan Liu, Nanjian Wu, Min Tian, Cong Shi
2023	J	`jnl`	Low-cost real-time VLSI system for high-accuracy optical flow estimation using biological motion features and random forests. Sci. China Inf. Sci. Cong Shi, Junxian He, Shrinivas J. Pundlik, Xichuan Zhou, Nanjian Wu, Gang Luo
2023	—	`conf`	MorphBungee: A 65nm 7.2mm A-SSCC Tengxiao Wang, Min Tian, Zhengqing Zhong, Haibing Wang, Junxian He, Fang Tang, Xichuan Zhou, Shuangming Yu, Nanjian Wu, Liyuan Liu, Cong Shi
2022	—	`conf`	A 0.004-mm APCCAS Yixi Li, Xinyu Shen, Zhaoyu Zhang, Guike Li, Tao Yin, Nan Qi, Jian Liu, Nanjian Wu, Liyuan Liu, Yong Chen, Zhao Zhang
2022	—	`conf`	A 0.006-mm APCCAS Zhaoyu Zhang, Xinyu Shen, Yixi Li, Guike Li, Nan Qi, Jian Liu, Nanjian Wu, Liyuan Liu, Yong Chen, Zhao Zhang
2022	—	`conf`	A 50-Gb/s NRZ Receiver Targeting Low-Latency Multi-Chip Module Optical I/O in 45-nm SOI CMOS. APCCAS Yihong Li, Sikai Chen, Yunqi Yang, Qianli Ma, Ming Zhong, Ziyi Lin, Leliang Li, Guike Li, Zhao Zhang, Liyuan Liu, Jian Liu, Nanjian Wu, Yong Chen, Qi Peng, Nan Qi
2022	J	`jnl`	A 50-Gb/s PAM-4 Silicon-Photonic Transmitter Incorporating Lumped-Segment MZM, Distributed CMOS Driver, and Integrated CDR. IEEE J. Solid State Circuits Qiwen Liao, Yuguang Zhang, Siyuan Ma, Lei Wang, Leliang Li, Guike Li, Zhao Zhang, Jian Liu, Nanjian Wu, Liyuan Liu, Yong Chen, Xi Xiao, Nan Qi
2022	J	`jnl`	A 56-Gb/s Reconfigurable Silicon-Photonics Transmitter Using High-Swing Distributed Driver and 2-Tap In-Segment Feed-Forward Equalizer in 65-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Jian He, Yuguang Zhang, Han Liu, Qiwen Liao, Zhao Zhang, Miaofeng Li, Fan Jiang, Jingbo Shi, Jian Liu, Nanjian Wu, Yong Chen, Patrick Yin Chiang, Ningmei Yu, Xi Xiao, Nan Qi
2022	—	`conf`	A 56Gb/s De-serializer with PAM-4 CDR for Chiplet Optical-I/O. ICTA Yunqi Yang, Ming Zhong, Qianli Ma, Ziyi Lin, Leliang Li, Guike Li, Liyuan Liu, Jian Liu, Nanjian Wu, Haikun Jia, Xinghui Liu, Nan Qi
2022	J	`jnl`	A High-Speed NMS Coprocessor for Lightweight Ship Detection Algorithm. IEEE Trans. Circuits Syst. II Express Briefs Ke Ning, Mingxin Zhao, Chunhe Yao, Xuemin Zheng, Mengmeng Xu, Nanjian Wu, Liyuan Liu, Shuangming Yu
2022	J	`jnl`	A Low-Cost FPGA Implementation of Spiking Extreme Learning Machine With On-Chip Reward-Modulated STDP Learning. IEEE Trans. Circuits Syst. II Express Briefs Zhen He, Cong Shi, Tengxiao Wang, Ying Wang, Min Tian, Xichuan Zhou, Ping Li, Liyuan Liu, Nanjian Wu, Gang Luo
2022	J	`jnl`	A Programmable and Flexible Vision Processor. IEEE Trans. Circuits Syst. II Express Briefs Qian Luo, Chunhe Yao, Ke Ning, Xuemin Zheng, Mingxin Zhao, Li Cheng, Shuangming Yu, Jian Liu, Nanjian Wu, Liyuan Liu
2022	J	`jnl`	A Provisional Labels-Reduced, Real-Time Connected Component Labeling Algorithm for Edge Hardware. IEEE Trans. Circuits Syst. II Express Briefs Hongtao Zhou, Runjiang Dou, Li Cheng, Jian Liu, Nanjian Wu
2022	—	`conf`	An 8-T Processing-in-Memory SRAM Cell-Based Pixel-Parallel Array Processor for Vision Chips. APCCAS Leyi Chen, Junxian He, Jianyi Yu, Haibing Wang, Jing Lu, Liyuan Liu, Nanjian Wu, Cong Shi, Min Tian
2022	J	`jnl`	Design of a PAM-4 VCSEL-Based Transceiver Front-End for Beyond-400G Short-Reach Optical Interconnects. IEEE Trans. Circuits Syst. I Regul. Pap. Jian He, Donglai Lu, Haiyun Xue, Sikai Chen, Han Liu, Leliang Li, Guike Li, Zhao Zhang, Jian Liu, Liyuan Liu, Nanjian Wu, Ningmei Yu, Fengman Liu, Xi Xiao, Yong Chen, Nan Qi
2022	J	`jnl`	Exploring Structural Sparsity in CNN via Selective Penalty. IEEE Trans. Circuits Syst. Video Technol. Mingxin Zhao, Junbo Peng, Shuangming Yu, Liyuan Liu, Nanjian Wu
2022	—	`conf`	Floorplanning and Power/Ground Network Design for A Programmable Vision Chip. ICTA Haozhe Xu, Siyuan Wei, Nan Qi, Peng Wu, Jian Liu, Nanjian Wu, Liyuan Liu, Shuangming Yu
2022	—	`conf`	MorphBungee: An Edge Neuromorphic Chip for High-Accuracy On-Chip Learning of Multiple-Layer Spiking Neural Networks. BioCAS Tengxiao Wang, Haibing Wang, Junxian He, Zhengqing Zhong, Fang Tang, Xichuan Zhou, Shuangming Yu, Liyuan Liu, Nanjian Wu, Min Tian, Cong Shi
2022	J	`jnl`	SiamMixer: A Lightweight and Hardware-Friendly Visual Object-Tracking Network. Sensors Li Cheng, Xuemin Zheng, Mingxin Zhao, Runjiang Dou, Shuangming Yu, Nanjian Wu, Liyuan Liu
2022	J	`jnl`	TripleBrain: A Compact Neuromorphic Hardware Core With Fast On-Chip Self-Organizing and Reinforcement Spike-Timing Dependent Plasticity. IEEE Trans. Biomed. Circuits Syst. Haibing Wang, Zhen He, Tengxiao Wang, Junxian He, Xichuan Zhou, Ying Wang, Liyuan Liu, Nanjian Wu, Min Tian, Cong Shi
2022	J	`jnl`	ViP: A Hierarchical Parallel Vision Processor for Hybrid Vision Chip. IEEE Trans. Circuits Syst. II Express Briefs Xuemin Zheng, Li Cheng, Mingxin Zhao, Qian Luo, Honglong Li, Runjiang Dou, Shuangming Yu, Nanjian Wu, Liyuan Liu
2021	—	`conf`	100Gb/s PAM-4 VCSEL Driver and TIA for Short-Reach 400G-1.6T Optical Interconnects. APCCAS Donglai Lu, Jian He, Weizhong Li, Sikai Chen, Jian Liu, Nanjian Wu, Ningmei Yu, Liyuan Liu, Yong Chen, Xi Xiao, Nan Qi
2021	—	`conf`	A 32×32 Array Terahertz Sensor in 65-nm CMOS Technology. ICTA Tong Fang, Min Liu, Liyuan Liu, Ziteng Cai, Runjiang Dou, Peng Feng, Nan Qi, Zhao Zhang, Jian Liu, Nanjian Wu
2021	—	`conf`	A 50Gb/s High-Efficiency Si-Photonic Transmitter With Lump-Segmented MZM and Integrated PAM4 CDR. CICC Qiwen Liao, Miaofeng Li, Zhao Zhang, Jian Liu, Nanjian Wu, Xi Xiao, Nan Qi
2021	J	`jnl`	A Compact High-Quality Image Demosaicking Neural Network for Edge-Computing Devices. Sensors Shuyu Wang, Mingxin Zhao, Runjiang Dou, Shuangming Yu, Liyuan Liu, Nanjian Wu
2021	J	`jnl`	A Cost-Efficient High-Speed VLSI Architecture for Spiking Convolutional Neural Network Inference Using Time-Step Binary Spike Maps. Sensors Ling Zhang, Jing Yang, Cong Shi, Yingcheng Lin, Wei He, Xichuan Zhou, Xu Yang, Liyuan Liu, Nanjian Wu
2021	—	`conf`	A Fast-Transient Capacitor-Less Low-Dropout Regulator for Wideband Optical Transceivers. ICTA Han Liu, Guike Li, Jian Liu, Nanjian Wu, Liyuan Liu, Yingtao Li, Nan Qi
2021	J	`jnl`	A Low-Cost High-Speed Object Tracking VLSI System Based on Unified Textural and Dynamic Compressive Features. IEEE Trans. Circuits Syst. II Express Briefs Wei He, Jie Zhang, Yingcheng Lin, Xichuan Zhou, Ping Li, Liyuan Liu, Nanjian Wu, Cong Shi
2021	—	`conf`	A Pixel-Parallel Array Processor without Computational Logic for Computational Image Sensors. ICTA Yingcheng Lin, Rui Li, Wei He, Xichuan Zhou, Junxian He, Ping Li, Liyuan Liu, Nanjian Wu, Cong Shi
2021	J	`jnl`	CompSNN: A lightweight spiking neural network based on spatiotemporally compressive spike features. Neurocomputing Tengxiao Wang, Cong Shi, Xichuan Zhou, Yingcheng Lin, Junxian He, Ping Gan, Ping Li, Ying Wang, Liyuan Liu, Nanjian Wu, Gang Luo
2021	J	`jnl`	DeepTempo: A Hardware-Friendly Direct Feedback Alignment Multi-Layer Tempotron Learning Rule for Deep Spiking Neural Networks. IEEE Trans. Circuits Syst. II Express Briefs Cong Shi, Tengxiao Wang, Junxian He, Jianghao Zhang, Liyuan Liu, Nanjian Wu
2021	—	`conf`	Pixel Design of Ultra-high Speed CMOS Image Sensor. ASICON Peng Feng, Liyuan Liu, Nanjian Wu
2021	—	`conf`	TripleBrain: An Edge Neuromorphic Architecture for High-accuracy Single-layer Spiking Neural Network with On-chip Self-organizing and Reinforcement Learning. ICTA Haibing Wang, Zhen He, Jinsong Rao, Tengxiao Wang, Junxian He, Min Tian, Xichuan Zhou, Liyuan Liu, Nanjian Wu, Cong Shi
2020	—	`conf`	A 28GBaud High-Swing Linear Mach-Zehnder Modulators Driver for PAM-4 and Coherent Optical Communications. ICTA Kai Hao, Jian He, Leliang Li, Shuangming Yu, Liyuan Liu, Jian Liu, Ningmei Yu, Nanjian Wu, Nan Qi
2020	J	`jnl`	A 50-Gb/s PAM4 Si-Photonic Transmitter With Digital-Assisted Distributed Driver and Integrated CDR in 40-nm CMOS. IEEE J. Solid State Circuits Qiwen Liao, Nan Qi, Miaofeng Li, Shang Hu, Jian He, Bozhi Yin, Jingbo Shi, Jian Liu, Patrick Yin Chiang, Xi Xiao, Nanjian Wu
2020	C	`conf`	A 50Gb/s PAM-4 Optical Receiver with Si-Photonic PD and Linear TIA in 40nm CMOS. ISCAS Yang Liu, Nan Qi, Xiuli Xu, Weizhong Li, Lei Wang, Minjia Chen, Qixiang Cheng, Jingbo Shi, Liyuan Liu, Jian Liu, Xi Xiao, Nanjian Wu
2020	—	`conf`	A Compact On-chip Analog Memory Cell for Storing TOF Image Signal in CMOS Process. ICTA Zhenhua Guo, Chao Gu, Shuangming Yu, Liyuan Liu, Jian Liu, Peng Feng, Nanjian Wu
2020	J	`jnl`	A Discrete-Time Audio ΔΣ Modulator Using Dynamic Amplifier With Speed Enhancement and Flicker Noise Reduction Techniques. IEEE J. Solid State Circuits Song Ma, Liyuan Liu, Tong Fang, Jian Liu, Nanjian Wu
2020	J	`jnl`	A High-Speed Low-Cost VLSI System Capable of On-Chip Online Learning for Dynamic Vision Sensor Data Classification. Sensors Wei He, Jinguo Huang, Tengxiao Wang, Yingcheng Lin, Junxian He, Xichuan Zhou, Ping Li, Ying Wang, Nanjian Wu, Cong Shi
2020	—	`conf`	A High-Speed Parallel FPGA Implementation of Harris Corner Detection. ICTA Hongtao Zhou, Runjiang Dou, Shuangming Yu, Nan Qi, Jian Liu, Nanjian Wu, Liyuan Liu
2020	—	`conf`	A High-speed Low-cost CNN Inference Accelerator for Depthwise Separable Convolution. ICTA Yingcheng Lin, Rui Li, Wei He, Xichuan Zhou, Junxian He, Ping Li, Ying Jiang, Liyuan Liu, Nanjian Wu, Cong Shi
2020	—	`conf`	A Method of Estimating FD Capacitance with Large Size Photodiode in High Speed Imaging (Invited Paper). ICTA Chao Gu, Zhenhua Guo, Shuangming Yu, Liyuan Liu, Jian Liu, Peng Feng, Nanjian Wu
2020	—	`conf`	A verification method for array-based vision chip using a fixed-point neural network simulation tool. LASCAS Mingxin Zhao, Xuemin Zheng, Ke Ning, Chunhe Yao, Qian Luo, Shuangming Yu, Liyuan Liu, Nanjian Wu
2020	J	`jnl`	Deterministic conversion rule for CNNs to efficient spiking convolutional neural networks. Sci. China Inf. Sci. Xu Yang, Zhongxing Zhang, Wenping Zhu, Shuangming Yu, Liyuan Liu, Nanjian Wu
2020	J	`jnl`	Quantizing Oriented Object Detection Network via Outlier-Aware Quantization and IoU Approximation. IEEE Signal Process. Lett. Mingxin Zhao, Ke Ning, Shuangming Yu, Liyuan Liu, Nanjian Wu
2020	J	`jnl`	TBC-Net: A real-time detector for infrared small target detection using semantic constraint. CoRR Mingxin Zhao, Li Cheng, Xu Yang, Peng Feng, Liyuan Liu, Nanjian Wu
2019	J	`jnl`	0.1-5 GHz wideband ΔΣ fractional-N frequency synthesiser for software-defined radio application. IET Circuits Devices Syst. Zhao Zhang, Jincheng Yang, Liyuan Liu, Nan Qi, Peng Feng, Jian Liu, Nanjian Wu
2019	—	`conf`	20, 000-fps Visual Motion Magnification on Pixel-parallel Vision Chip. ASICON Junxian He, Xichuan Zhou, Yingcheng Lin, Chonglei Sun, Cong Shi, Nanjian Wu, Gang Luo
2019	J	`jnl`	A 0.45-to-1.8 GHz synthesized injection-locked bang-bang phase locked loop with fine frequency tuning circuits. Sci. China Inf. Sci. Jincheng Yang, Zhao Zhang, Nan Qi, Liyuan Liu, Jian Liu, Nanjian Wu
2019	—	`conf`	A 8-b 1GS/s 2b/cycle SAR ADC in 28-nm CMOS. APCCAS Song Ma, Liyuan Liu, Jian Liu, Nanjian Wu
2019	J	`jnl`	An 18-23 GHz 57.4-fs RMS Jitter -253.5-dB FoM Sub-Harmonically Injection-Locked All-Digital PLL With Single-Ended Injection Technique and ILFD Aided Adaptive Injection Timing Alignment Technique. IEEE Trans. Circuits Syst. I Regul. Pap. Zhao Zhang, Jincheng Yang, Liyuan Liu, Nan Qi, Peng Feng, Jian Liu, Nanjian Wu
2019	—	`conf`	Design of High-Speed Drivers for 56Gb/s PAM4 Optical Communications in CMOS. ASICON Nan Qi, Nanjian Wu
2019	—	`conf`	Efficient Reservoir Encoding Method for Near-Sensor Classification with Rate-Coding Based Spiking Convolutional Neural Networks. ISNN (2) Xu Yang, Shuangming Yu, Liyuan Liu, Jian Liu, Nanjian Wu
2019	—	`conf`	High-speed Classification of AER Data Based on a Low-cost Hardware System. ASICON Jinguo Huang, Yingcheng Lin, Wei He, Xichuan Zhou, Cong Shi, Nanjian Wu, Gang Luo
2019	J	`jnl`	High-speed target tracking system based on multi-interconnection heterogeneous processor and multi-descriptor algorithm. Sci. China Inf. Sci. Jiaqing Wang, Yongxing Yang, Liyuan Liu, Nanjian Wu
2019	J	`jnl`	Single event upset failure probability evaluation and periodic scrubbing techniques for hierarchical parallel vision processors. IEICE Electron. Express Qian Di, Zhongxing Zhang, Honglong Li, Zhao Zhang, Peng Feng, Nanjian Wu
2018	J	`jnl`	A 0.9-2.25-GHz Sub-0.2-mW/GHz Compact Low-Voltage Low-Power Hybrid Digital PLL With Loop Bandwidth-Tracking Technique. IEEE Trans. Very Large Scale Integr. Syst. Zhao Zhang, Jincheng Yang, Liyuan Liu, Peng Feng, Jian Liu, Nanjian Wu
2018	—	`conf`	A 25 fps 32 × 24 Digital CMOS Terahertz Image Sensor. A-SSCC Tong Fang, Runjiang Dou, Liyuan Liu, Jian Liu, Nanjian Wu
2018	—	`conf`	A Fast Auto-Frequency Calibration Technique for Wideband PLL with Wide Reference Frequency Range. A-SSCC Zhao Zhang, Jincheng Yang, Liyuan Liu, Nan Qi, Peng Feng, Jian Liu, Nanjian Wu
2018	J	`jnl`	A Heterogeneous Parallel Processor for High-Speed Vision Chip. IEEE Trans. Circuits Syst. Video Technol. Jie Yang, Yongxing Yang, Zhe Chen, Liyuan Liu, Jian Liu, Nanjian Wu
2018	J	`jnl`	Neuromorphic vision chips. Sci. China Inf. Sci. Nanjian Wu
2017	J	`jnl`	A 1.25-to-6.25 GHz -237.2-dB FOM wideband self-biased PLL for multi-rate serial link data transmitter. IEICE Electron. Express Zhao Zhang, Jincheng Yang, Liyuan Liu, Peng Feng, Jian Liu, Nanjian Wu
2017	—	`conf`	A 18-to-23 GHz -253.5dB-FoM sub-harmonically injection-locked ADPLL with ILFD aided adaptive injection timing alignment technique. A-SSCC Zhao Zhang, Jincheng Yang, Liyuan Liu, Peng Feng, Jian Liu, Nanjian Wu
2017	J	`jnl`	A 2.4-3.6-GHz Wideband Subharmonically Injection-Locked PLL With Adaptive Injection Timing Alignment Technique. IEEE Trans. Very Large Scale Integr. Syst. Zhao Zhang, Liyuan Liu, Peng Feng, Nanjian Wu
2017	—	`conf`	A low-power 2.4GHz ZigBee transceiver with inductor-less RF front-end for IoT applications. MWSCAS Bing Xia, Nan Qi, Liyuan Liu, Nanjian Wu
2017	—	`conf`	Detection of 3.0 THz wave with a detector in 65 nm standard CMOS process. A-SSCC Tong Fang, Zhao-Yang Liu, Liyuan Liu, Yuan-Yuan Li, Jun-Qi Liu, Jian Liu, Nanjian Wu
2017	J	`jnl`	High-Speed Target Tracking System Based on a Hierarchical Parallel Vision Processor and Gray-Level LBP Algorithm. IEEE Trans. Syst. Man Cybern. Syst. Yongxing Yang, Jie Yang, Liyuan Liu, Nanjian Wu
2017	J	`jnl`	High-speed visual target tracking with mixed rotation invariant description and skipping searching. Sci. China Inf. Sci. Yongxing Yang, Jie Yang, Zhongxing Zhang, Liyuan Liu, Nanjian Wu
2017	J	`jnl`	Terahertz detector for imaging in 180-nm standard CMOS process. Sci. China Inf. Sci. Zhao-Yang Liu, Liyuan Liu, Zhao Zhang, Jian Liu, Nanjian Wu
2016	J	`jnl`	A 256×256 time-of-flight image sensor based on center-tap demodulation pixel structure. Sci. China Inf. Sci. Zhe Chen, Shan Di, Zhongxiang Cao, Qi Qin, Fei Ji, Liyuan Liu, Nanjian Wu
2016	—	`conf`	A 91.2dB SNDR 66.2fJ/conv. dynamic amplifier based 24kHz ΔΣ modulator. A-SSCC Beichen Zhang, Runjiang Dou, Liyuan Liu, Nanjian Wu
2015	—	`conf`	A 1-V 5.2-5.7 GHz low noise sub-sampling phase locked loop in 0.18 μm CMOS. ASICON Jincheng Yang, Zhao Zhang, Peng Feng, Liyuan Liu, Nanjian Wu
2015	—	`conf`	A fully-integrated 860-GHz CMOS terahertz sensor. A-SSCC Zhao-Yang Liu, Liyuan Liu, Jie Yang, Nanjian Wu
2015	J	`jnl`	A low power global shutter pixel with extended FD voltage swing range for large format high speed CMOS image sensor. Sci. China Inf. Sci. Yangfan Zhou, Zhongxiang Cao, Ye Han, Quanliang Li, Cong Shi, Runjiang Dou, Qi Qin, Jian Liu, Nanjian Wu
2015	—	`conf`	A novel vision chip architecture for image recognition based on convolutional neural network. ASICON Honglong Li, Zhongxing Zhang, Jie Yang, Liyuan Liu, Nanjian Wu
2015	—	`conf`	An efficient layered ABV methodology for vision system on chip based on heterogeneous parallel processors. ASICON Victor Nshunguyimfura, Jie Yang, Liyuan Liu, Nanjian Wu
2015	—	`conf`	High-speed object detection based on a hierarchical parallel vision chip. ASICON Zhongxing Zhang, Jie Yang, Honglong Li, Liyuan Liu, Jian Liu, Nanjian Wu
2014	—	`conf`	7.3 A 1000fps vision chip based on a dynamically reconfigurable hybrid architecture comprising a PE array and self-organizing map neural network. ISSCC Cong Shi, Jie Yang, Ye Han, Zhongxiang Cao, Qi Qin, Liyuan Liu, Nanjian Wu, Zhihua Wang
2014	J	`jnl`	A 1000 fps Vision Chip Based on a Dynamically Reconfigurable Hybrid Architecture Comprising a PE Array Processor and Self-Organizing Map Neural Network. IEEE J. Solid State Circuits Cong Shi, Jie Yang, Ye Han, Zhongxiang Cao, Qi Qin, Liyuan Liu, Nanjian Wu, Zhihua Wang
2014	J	`jnl`	A 2.4 GHz low power CMOS transceiver for LR-WPAN applications. Sci. China Inf. Sci. Weiyang Liu, Jingjing Chen, Xiaodong Liu, Haiyong Wang, Nanjian Wu
2014	J	`jnl`	A high speed 1000 fps CMOS image sensor with low noise global shutter pixels. Sci. China Inf. Sci. Yangfan Zhou, Zhongxiang Cao, Qi Qin, Quanliang Li, Cong Shi, Nanjian Wu
2014	J	`jnl`	A high speed multi-level-parallel array processor for vision chips. Sci. China Inf. Sci. Cong Shi, Jie Yang, Nanjian Wu, Zhihua Wang
2014	J	`jnl`	A massively parallel keypoint detection and description (MP-KDD) algorithm for high-speed vision chip. Sci. China Inf. Sci. Cong Shi, Jie Yang, Liyuan Liu, Nanjian Wu, Zhihua Wang
2014	—	`conf`	A novel 2.4-to-3.6 GHz wideband subharmonically injection-locked PLL with adaptively-aligned injection timing. A-SSCC Zhao Zhang, Liyuan Liu, Nanjian Wu
2013	—	`conf`	A 2.4 GHz energy-efficient 18-Mbps FSK transmitter in 0.18 μm CMOS. CICC Jingjing Chen, Weiyang Liu, Peng Feng, Haiyong Wang, Nanjian Wu
2013	J	`jnl`	A Low Power 2.4 GHz RF Transceiver for ZigBee Applications. J. Circuits Syst. Comput. Weiyang Liu, Jingjing Chen, Haiyong Wang, Nanjian Wu
2013	—	`conf`	A novel architecture of local memory for programmable SIMD vision chip. ASICON Zhe Chen, Jie Yang, Cong Shi, Nanjian Wu
2012	—	`conf`	Ultra-low-power RF transceivers for WBANs in medical applications. NEWCAS Nanjian Wu, Qi Zhang
2011	J	`jnl`	A 2.4-GHz Energy-Efficient Transmitter for Wireless Medical Applications. IEEE Trans. Biomed. Circuits Syst. Qi Zhang, Peng Feng, Zhiqing Geng, Xiaozhou Yan, Nanjian Wu
2011	—	`conf`	Design of four-transistor Pixel for high speed CMOS image. ASICON Yangfan Zhou, Zhongxiang Cao, Quanliang Li, Qi Qin, Nanjian Wu
2010	C	`conf`	A novel RFID tag chip with temperature sensor in standard CMOS process. ISCAS Qi Zhang, Peng Feng, Shenghua Zhou, Zhiqing Geng, Nanjian Wu
2009	C	`conf`	A Smart Frequency Presetting Technique for Fast Lock-in LC-PLL Frequency Synthesizer. ISCAS Xiaozhou Yan, Xiaofei Kuang, Nanjian Wu
2009	—	`conf`	An accurate and fast behavioral model for PLL Frequency Synthesizer phase noise/spurs prediction. CICC Xiaozhou Yan, Xiaofei Kuang, Nanjian Wu
2009	—	`conf`	An ultra low power non-volatile memory in standard CMOS process for passive RFID tags. CICC Peng Feng, Yunlong Li, Nanjian Wu
2007	C	`conf`	A LO-leakage auto-calibrated CMOS IEEE802.11b/g WLAN transceiver. ISCAS Haiyong Wang, Guoliang Shou, Nanjian Wu
2006	—	`conf`	A fast-settling PLL frequency synthesizer with direct frequency presetting. ISSCC Xiaofei Kuang, Nanjian Wu
2006	C	`conf`	An adaptive frequency synthesizer architecture reducing reference sidebands. ISCAS Haiyong Wang, Guoliang Shou, Nanjian Wu