Nanditha P. Rao

14 papers C 4Journal 4Unranked 6

Year	Rank	Type	Title / Venue / Authors
2024	—	`conf`	ConvMap: Boosting Convolution Throughput on FPGAs with Efficient Resource Mapping. IPDPS (Workshops) Shubhayu Das, Nanditha P. Rao, Sharad Sinha
2023	—	`conf`	MCSim: A Multi-Core Cache Simulator Accelerated on a Resource-constrained FPGA. ACM Great Lakes Symposium on VLSI Shivani Shah, Nanditha P. Rao
2022	C	`conf`	An Automated Approach to Compare Bit Serial and Bit Parallel In-Memory Computing for DNNs. ISCAS Alok Parmar, Kailash Prasad, Nanditha P. Rao, Joycee Mekie
2022	C	`conf`	An FPGA based Tiled Systolic Array Generator to Accelerate CNNs. DSD Veerendra S. Devaraddi, Nanditha P. Rao
2022	—	`conf`	FastMem: A Fast Architecture-aware Memory Layout Design. ISQED Alok Parmar, Kailash Prasad, Nanditha P. Rao, Joycee Mekie
2021	C	`conf`	Cache-accel: FPGA Accelerated Cache Simulator with Partially Reconfigurable Prefetcher. DSD Shivani Shah, Vaibhavi Mathur, Sahithi Meenakshi Vutakuru, Kavya Borra, Nanditha P. Rao
2021	—	`conf`	FPGA Accelerated Parameterized Cache Simulator. ISQED Shivani Shah, Sahithi Meenakshi Vutakuru, Nanditha P. Rao
2021	—	`conf`	Flush-Reload Attack and its Mitigation on an FPGA Based Compressed Cache Design. ISQED Prashant Mata, Nanditha P. Rao
2021	—	`conf`	Variable Bit-Precision Vector Extension for RISC-V Based Processors. MCSoC Risikesh RK, Sharad Sinha, Nanditha P. Rao
2018	J	`jnl`	Quantification of the likelihood of single event multiple transients in logic circuits in bulk CMOS technology. Microelectron. J. Nanditha P. Rao, Madhav P. Desai
2017	J	`jnl`	Neutron-induced strike: Study of multiple node charge collection in 14nm FinFETs. CoRR Nanditha P. Rao, Madhav P. Desai
2016	J	`jnl`	Higher likelihood of multiple bit-flips due to neutron-induced strikes on logic gates. CoRR Nanditha P. Rao, Madhav P. Desai
2015	C	`conf`	A Detailed Characterization of Errors in Logic Circuits due to Single-Event Transients. DSD Nanditha P. Rao, Madhav P. Desai
2014	J	`jnl`	On the likelihood of multiple bit upsets in logic circuits. CoRR Nanditha P. Rao, Shahbaz Sarik, Madhav P. Desai