Nan Sun - RankMe

185 papers A* 8A 6B 1C 15Journal 70Unranked 85

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	21.8 A CMOS Hybrid Common-Gate Current-Integrating Sampler with <37dB SNDR Across 51GHz BW in a 128GS/s Front-End. ISSCC Jun Dai, Yi Zhong, Yunsong Tao, Aodong Zhang, Mingtao Zhan, Hao Zhang, Lu Jie, Nan Sun
2026	—	`conf`	A 13b 500MS/s 94dB-SFDR Resistive-Input Pipelined-SAR ADC with Linear and Efficient Current-Buffer-Based Integrating Sampler. ISSCC Xiyu He, Mingyang Gu, Yunsong Tao, Siyu Huang, Zhishuai Zhang, Yi Zhong, Nan Sun, Lu Jie
2026	J	`jnl`	A 16-bit 10-GS/s DAC Achieving >65-dBc SFDR and <-75-dBc IM3 up to the Nyquist in 28-nm CMOS. IEEE J. Solid State Circuits Chengyu Huang, Kezhuo Ma, Chenxi Jia, Sihao Chen, Ruiqi Zhao, Xinyu Zhou, Nan Sun, Huazhong Yang, Xueqing Li
2026	J	`jnl`	A 40-nm 26.4 mW, 18.6 MS/s Image Reconstruction Processor for IoT Compressive Sensing. IEEE J. Solid State Circuits Yu-Cheng Lin, Chanmin Park, Wenda Zhao, Nan Sun, Youngcheol Chae, Chia-Hsiang Yang
2026	—	`conf`	A 98.5dB-SNDR 250kHz-BW 1V-Supply Continuous-Time Zoom ADC with Smart-Tracking and Floating-Tail-Resistor Linearized Gm-C Loop Filter. ISSCC Chaoyang Xing, Yilu Cui, Sining Pan, Yi Zhong, Nan Sun, Lu Jie
2026	A*	`conf`	AMS-IO-Bench and AMS-IO-Agent: Benchmarking and Structured Reasoning for Analog and Mixed-Signal Integrated Circuit Input/Output Design. AAAI Zhishuai Zhang, Xintian Li, Shilong Liu, Aodong Zhang, Lu Jie, Nan Sun
2026	J	`jnl`	Multi-Perspective Natural Vector: A Novel Method for Viral Sequence Feature Extraction. J. Comput. Biol. Xiang Shi, Jiayi Kang, Nan Sun, Xin Zhao, Stephen S.-T. Yau
2025	—	`conf`	24.1 A 12b 3GS/s Pipelined ADC with Gated-LMS-Based Piecewise-Linear Nonlinearity Calibration. ISSCC Mingyang Gu, Yi Zhong, Lu Jie, Nan Sun
2025	—	`conf`	3.4: A CMOS Operational Amplifier Achieving ±5.8µV 3σ Offset and ±88nV/°C 3σ Offset Drift Using an on-Chip Heater-Based Self-Trimming Technique. ISSCC Aodong Zhang, Mingtao Zhan, Mengying Chen, Yi Zhong, Lu Jie, Nan Sun, Qinwen Fan
2025	—	`conf`	A 0.16mm CICC Heyang Zhao, Yuxuan He, Yunsong Tao, Zhishuai Zhang, Yong Chen, Yi Zhong, Lu Jie, Nan Sun
2025	J	`jnl`	A 1-GS/s 11-b Time-Interleaved SAR ADC With Robust, Fast, and Accurate Autocorrelation-Based Background Timing-Skew Calibration. IEEE J. Solid State Circuits Mingyang Gu, Yunsong Tao, Xiyu He, Yi Zhong, Lu Jie, Nan Sun
2025	—	`conf`	A 22.4-25.6GHz Ping-Pong Sub-Sampling PLL Featuring Unified Supply Voltage and Balanced 2 CICC Yunbo Huang, Zunsong Yang, Hongyu Ren, Rui Paulo Martins, Yan Lu, Nan Sun, Nan Qi, Yong Chen
2025	J	`jnl`	A 28-nm 8-Bit 16-GS/ DAC With >60 dBc/>40 dBc SFDR Up To 2.3 GHz/5.4 GHz Using 4-Channel NRZ-Output-Overlapped Time-Interleaving. IEEE Trans. Circuits Syst. II Express Briefs Sihao Chen, Chengyu Huang, Limeng Sun, Yang Liu, Wenjun Tang, Jiaxuan Fan, Nan Sun, Yong Chen, Huazhong Yang, Xueqing Li
2025	J	`jnl`	A 470 μW 20 kHz-BW 107.3 dB-SNDR Nested CT DSM Using Negative-R-Based Cross-RC Integrator and Weighted Multi-Threshold MSB-Pass Quantizer. IEEE Trans. Circuits Syst. I Regul. Pap. Jing Jin, Meng Xu, Yuekang Guo, Xiaoming Liu, Nan Sun, Jianjun Zhou
2025	—	`conf`	A 70dB SNDR 80MHz BW Filter-Embedded Pipeline-SAR ADC Achieving 172dB FoMs with Progressive Conversion and Floating-Charge-Transfer Amplifier. ISSCC Siyu Huang, Zhishuai Zhang, Xiyu He, Mingyang Gu, Yunsong Tao, Yi Zhong, Nan Sun, Lu Jie
2025	C	`conf`	A 75-MHz-BW 3rd-order Time-Interleaved Noise-Shaping SAR ADC with Shared EF-CIFF Loop Filter and Ring Buffer. ISCAS Xiyu He, Yi Zhong, Nan Sun, Lu Jie
2025	C	`conf`	A Hierarchical Compilation Method for Programmable Analog-to-Digital Converter Arrays. ISCAS Zhishuai Zhang, Siyu Huang, Yi Zhong, Nan Sun, Lu Jie
2025	—	`conf`	A Power-Efficient Jitter-Insensitive 3.2GHz 1-bit CT ΔΣ ADC with Direct Charge Dump Feedback. CICC Yanquan Luo, Lu Jie, Nan Sun
2025	J	`jnl`	AMS-IO-Bench and AMS-IO-Agent: Benchmarking and Structured Reasoning for Analog and Mixed-Signal Integrated Circuit Input/Output Design. CoRR Zhishuai Zhang, Xintian Li, Shilong Liu, Aodong Zhang, Lu Jie, Nan Sun
2025	—	`conf`	An 8b 10GS/s 2-Channel Time-Interleaved Pipelined ADC with Concurrent Residue Transfer and Quantization, and Automatic Buffer Power Gating. ISSCC Yunsong Tao, Mingtao Zhan, Mingyang Gu, Xiyu He, Yuxuan He, Zhishuai Zhang, Yi Zhong, Lu Jie, Nan Sun
2025	J	`jnl`	First-In-Last-Out Data Weighted Averaging Technique for Multi-Bit ΔΣ ADCs. IEEE Trans. Circuits Syst. II Express Briefs Xing Wang, Chaoyang Xing, Yi Zhong, Lu Jie, Nan Sun
2025	C	`conf`	Live Demonstration: A Programmable A/D Converter Array with Interactive Compiler. ISCAS Zhishuai Zhang, Chitian Yuan, Jiantao Li, Kun Lin, Yi Zhong, Nan Sun, Lu Jie
2025	J	`jnl`	Programmable Analog-to-Digital Converter Array Supporting Architecture Restructuring and Mode Concurrency. IEEE Trans. Circuits Syst. I Regul. Pap. Zhishuai Zhang, Mingtao Zhan, Zijie Gao, Siyu Huang, Mingyang Gu, Yunsong Tao, Xiyu He, Chitian Yuan, Yi Zhong, Nan Sun, Lu Jie
2025	J	`jnl`	scMFF: a machine learning framework with multiple feature fusion strategies for cell type identification. BMC Bioinform. Nan Sun, Yu Wang, Xiang Shi, Dengcheng Yang, Rongling Wu, Stephen S.-T. Yau
2024	—	`conf`	22.4 A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Offset Calibration. ISSCC Yunsong Tao, Mingyang Gu, Baoyong Chi, Yi Zhong, Lu Jie, Nan Sun
2024	—	`conf`	9.3 A 71dB SNDR 200MHz BW Interleaved Pipe-SAR ADC with a Shared Residue Integrating Amplifier Achieving 173dB FoMs. ISSCC Xiyu He, Mingyang Gu, Hanjun Jiang, Yi Zhong, Nan Sun, Lu Jie
2024	J	`jnl`	A 0.004-mm IEEE J. Solid State Circuits Mingtao Zhan, Lu Jie, Xiyuan Tang, Yi Zhong, Nan Sun
2024	—	`conf`	A 1.2GS/s 11b Time-Interleaved SAR ADC with Low-Cost Derivative-Based Background Timing-Skew Calibration and Variable-Load Comparators. A-SSCC Mingyang Gu, Yunsong Tao, Xiyu He, Yi Zhong, Lu Jie, Nan Sun
2024	—	`conf`	A 16-bit 10-GS/s Calibration-Free DAC Achieving <-77dBc IM3 up to 4.95GHz in 28nm CMOS. CICC Chengyu Huang, Kezhuo Ma, Sihao Chen, Jiaxuan Fan, Nan Sun, Huazhong Yang, Xueqing Li
2024	—	`conf`	A 470μW 20kHz-BW 107.3dB-SNDR Nested CT DSM Employing Negative-R-Based Cross-RC Filter and Weighted Multi-Threshold MSB-Pass Quantizer. CICC Jing Jin, Yuekang Guo, Meng Xu, Xiaoming Liu, Nan Sun, Jianjun Zhou
2024	—	`conf`	A 92.9dB-SNDR 178.2dB-FoMs SAR ADC with kT/C noise cancellation and FIA. ICTA Zijie Gao, Yi Zhong, Lu Jie, Nan Sun
2024	C	`conf`	A Dithered-Digital-Mixing Background Timing-Skew Calibration Method for Time-Interleaved ADCs. ISCAS Yunsong Tao, Yi Zhong, Jin Shao, Changyou Men, Lu Jie, Nan Sun
2024	J	`jnl`	An Energy-Efficient Computing-in-Memory NN Processor With Set-Associate Blockwise Sparsity and Ping-Pong Weight Update. IEEE J. Solid State Circuits Jinshan Yue, Yongpan Liu, Xiaoyu Feng, Yifan He, Jingyu Wang, Zhe Yuan, Mingtao Zhan, Jiaxin Liu, Jian-Wei Su, Yen-Lin Chung, Ping-Chun Wu, Li-Yang Hong, Meng-Fan Chang, Nan Sun, Chunmeng Dou, Xueqing Li, Ming Liu, Huazhong Yang
2024	J	`jnl`	Mitigating Sampling Noise for Energy-Efficient ADCs: A Tutorial Brief. IEEE Trans. Circuits Syst. II Express Briefs Chang Liu, Jiaxin Liu, Nan Sun
2023	—	`conf`	A 0.021mm ESSCIRC Chaoyang Xing, Yi Zhong, Nan Sun, Lu Jie
2023	—	`conf`	A 0.69-Noise-Efficiency-Factor 4 x-Current-Reuse Dynamic Comparator with A Stacking FIA. CICC Haoyu Zhuang, Nan Sun, Yirui Cao, Linzhi Tao, Qiang Li
2023	J	`jnl`	A 10-mW 10-ENoB 1-GS/s Ring-Amp-Based Pipelined TI-SAR ADC With Split MDAC and Switched Reference Decoupling Capacitor. IEEE J. Solid State Circuits Mingtao Zhan, Lu Jie, Yi Zhong, Nan Sun
2023	—	`conf`	A 10mW 10-ENOB 1GS/s Ring-Amp-Based Pipelined TI-SAR ADC with Split MDAC and Switched Reference Decoupling Capacitor. ISSCC Mingtao Zhan, Lu Jie, Nan Sun
2023	—	`conf`	A 12b 1GS/s Pipelined ADC with Digital Background Calibration of Inter-stage Gain, Capacitor Mismatch, and Kick-back Errors. ESSCIRC Mingyang Gu, Yi Zhong, Lu Jie, Nan Sun
2023	J	`jnl`	A 16-Bit 4.0-GS/s Calibration-Free 65 nm DAC Achieving >70 dBc SFDR and < -80 dBc IM3 Up to 1 GHz With Enhanced Constant-Switching-Activity Data-Weighted-Averaging. IEEE Trans. Circuits Syst. I Regul. Pap. Yushen Fu, Chengyu Huang, Longqiang Lai, Nan Sun, Xueqing Li, Huazhong Yang
2023	—	`conf`	A 1GS/s6-Core Programmable A/D Converter Array Supporting Architecture Restructuring and Multitasking. CICC Zhishuai Zhang, Zijie Gao, Siyu Huang, Nan Sun, Lu Jie
2023	—	`conf`	A 26.4mW, 18.6MS/s Image Reconstruction Processor for IoT Compressive Sensing. VLSI Technology and Circuits Yu-Cheng Lin, Chanmin Park, Wenda Zhao, Nan Sun, Youngcheol Chae, Chia-Hsiang Yang
2023	—	`conf`	A 3.7mW 11b 1GS/s Time-Interleaved SAR ADC with Robust One-Stage Correlation-Based Background Timing-Skew Calibration. ESSCIRC Mingyang Gu, Yunsong Tao, Xiyu He, Yi Zhong, Lu Jie, Nan Sun
2023	J	`jnl`	A 4-Bit Mixed-Signal MAC Macro With One-Shot ADC Conversion. IEEE J. Solid State Circuits Xiangxing Yang, Nan Sun
2023	—	`conf`	A 5.6-89.9TOPS/W Heterogeneous Computing-in-Memory SoC with High-Utilization Producer-Consumer Architecture and High-Frequency Read-Free CIM Macro. VLSI Technology and Circuits Jinshan Yue, Mingtao Zhan, Zi Wang, Yifan He, Yaolei Li, Songming Yu, Wenyu Sun, Lu Jie, Chunmeng Dou, Xueqing Li, Nan Sun, Huazhong Yang, Ming Liu, Yongpan Liu
2023	J	`jnl`	A Bandwidth-Adaptive Pipelined SAR ADC With Three-Stage Cascoded Floating Inverter Amplifier. IEEE J. Solid State Circuits Xiyuan Tang, Xiangxing Yang, Jiaxin Liu, Zongnan Wang, Wei Shi, David Z. Pan, Nan Sun
2023	—	`conf`	A Fully-Dynamic kT/C-Noise-Canceled SAR ADC with Trimming-Free Dynamic Amplifier. CICC Haoyu Zhuang, Nan Sun, Linzhi Tao, Yizhan Li, Oiang Li
2023	J	`jnl`	A Power-Efficient 13-Tap FIR Filter and an IIR Filter Embedded in a 10-Bit SAR ADC. IEEE Trans. Circuits Syst. I Regul. Pap. Xin Xin, Linxiao Shen, Xiyuan Tang, Yi Shen, Jueping Cai, Xingyuan Tong, Nan Sun
2023	—	`conf`	An 80.2-to-89.1dB-SNDR 24k-to-200kHz-BW VCO-Based Synthesized ?S ADC with 105dB SFDR in 28-nm CMOS. CICC Yi Zhong, Mingtao Zhan, Wei Wang, Xiyuan Tang, Lu Jie, Nan Sun
2023	J	`jnl`	An In-Memory-Computing Charge-Domain Ternary CNN Classifier. IEEE J. Solid State Circuits Xiangxing Yang, Keren Zhu, Xiyuan Tang, Meizhi Wang, Mingtao Zhan, Nanshu Lu, Jaydeep P. Kulkarni, David Z. Pan, Yongpan Liu, Nan Sun
2023	A*	`conf`	LeCA: In-Sensor Learned Compressive Acquisition for Efficient Machine Vision on the Edge. ISCA Tianrui Ma, Adith Jagadish Boloor, Xiangxing Yang, Weidong Cao, Patrick Williams, Nan Sun, Ayan Chakrabarti, Xuan Zhang
2022	—	`conf`	A 0.004mm ISSCC Mingtao Zhan, Lu Jie, Xiyuan Tang, Nan Sun
2022	—	`conf`	A 0.014mm ISSCC Lu Jie, Mingtao Zhan, Xiyuan Tang, Nan Sun
2022	—	`conf`	A 0.37mm CICC Wei Shi, Xing Wang, Xiyuan Tang, Abhishek Mukherjee, Raviteja Theertham, Shanthi Pavan, Lu Jie, Nan Sun
2022	J	`jnl`	A 10-bit 100-MS/s SAR ADC With Always-On Reference Ripple Cancellation. IEEE Trans. Circuits Syst. I Regul. Pap. Yi Shen, Xiyuan Tang, Xin Xin, Shubin Liu, Zhangming Zhu, Nan Sun
2022	C	`conf`	A Fast Converging Correlation-Based Background Timing Skew Calibration Technique by Digital Windowing for Time-Interleaved ADCs. ISCAS Yunsong Tao, Kareem Ragab, Jin Shao, Pengpeng Chen, Yi Zhong, Lu Jie, Nan Sun
2022	C	`conf`	A Second-Order VCO-Based ΔΣ ADC with Fully Digital Feedback Summation. ISCAS Chaoyang Xing, Yi Zhong, Jin Shao, Pengpeng Chen, Lu Jie, Nan Sun
2022	J	`jnl`	An Efficient Analog Circuit Sizing Method Based on Machine Learning Assisted Global Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ahmet Faruk Budak, Miguel Gandara, Wei Shi, David Z. Pan, Nan Sun, Bo Liu
2022	—	`conf`	Generative-Adversarial-Network-Guided Well-Aware Placement for Analog Circuits. ASP-DAC Keren Zhu, Hao Chen, Mingjie Liu, Xiyuan Tang, Wei Shi, Nan Sun, David Z. Pan
2022	J	`jnl`	Low-Power SAR ADC Design: Overview and Survey of State-of-the-Art Techniques. IEEE Trans. Circuits Syst. I Regul. Pap. Xiyuan Tang, Jiaxin Liu, Yi Shen, Shaolan Li, Linxiao Shen, Arindam Sanyal, Kareem Ragab, Nan Sun
2022	—	`conf`	RobustAnalog: Fast Variation-Aware Analog Circuit Design Via Multi-task RL. MLCAD Wei Shi, Hanrui Wang, Jiaqi Gu, Mingjie Liu, David Z. Pan, Song Han, Nan Sun
2022	J	`jnl`	RobustAnalog: Fast Variation-Aware Analog Circuit Design Via Multi-task RL. CoRR Wei Shi, Hanrui Wang, Jiaqi Gu, Mingjie Liu, David Z. Pan, Song Han, Nan Sun
2021	—	`conf`	10.4 A 3.7mW 12.5MHz 81dB-SNDR 4th-Order CTDSM with Single-OTA and 2nd-Order NS-SAR. ISSCC Wei Shi, Jiaxin Liu, Abhishek Mukherjee, Xiangxing Yang, Xiyuan Tang, Linxiao Shen, Wenda Zhao, Nan Sun
2021	—	`conf`	27.1 A 250kHz-BW 93dB-SNDR 4 ISSCC Jiaxin Liu, Dengquan Li, Yi Zhong, Xiyuan Tang, Nan Sun
2021	—	`conf`	A 0.4-to-40MS/s 75.7dB-SNDR Fully Dynamic Event-Driven Pipelined ADC with 3-Stage Cascoded Floating Inverter Amplifier. ISSCC Xiyuan Tang, Xiangxing Yang, Jiaxin Liu, Wei Shi, David Z. Pan, Nan Sun
2021	—	`conf`	A 16-Bit 4.0-GS/s Calibration-Free 65nm DAC with >70dBc SFDR and <-80dBc IM3 up to 1GHz Using Constant-Activity Element Switching. ESSCIRC Chengyu Huang, Yushen Fu, Zekun Yang, Yang Liu, Nan Sun, Xueqing Li, Huazhong Yang
2021	—	`conf`	A 2.75-to-75.9TOPS/W Computing-in-Memory NN Processor Supporting Set-Associate Block-Wise Zero Skipping and Ping-Pong CIM with Simultaneous Computation and Weight Updating. ISSCC Jinshan Yue, Xiaoyu Feng, Yifan He, Yuxuan Huang, Yipeng Wang, Zhe Yuan, Mingtao Zhan, Jiaxin Liu, Jian-Wei Su, Yen-Lin Chung, Ping-Chun Wu, Li-Yang Hung, Meng-Fan Chang, Nan Sun, Xueqing Li, Huazhong Yang, Yongpan Liu
2021	J	`jnl`	A 3-Phase Resonant Switched-Capacitor Converter for Data Center 48-V Rack Power Distribution. IEEE Trans. Circuits Syst. I Regul. Pap. Chuang Wang, Yan Lu, Nan Sun, Rui Paulo Martins
2021	J	`jnl`	A 51-pJ/Pixel 33.7-dB PSNR 4× Compressive CMOS Image Sensor With Column-Parallel Single-Shot Compressive Sensing. IEEE J. Solid State Circuits Chanmin Park, Wenda Zhao, Injun Park, Nan Sun, Youngcheol Chae
2021	J	`jnl`	A 74.5-dB Dynamic Range 10-MHz BW CT-ΔΣ ADC With Distributed-Input VCO and Embedded Capacitive-π Network in 40-nm CMOS. IEEE J. Solid State Circuits Abhishek Mukherjee, Miguel Gandara, Xiangxing Yang, Linxiao Shen, Xiyuan Tang, Chen-Kai Hsu, Nan Sun
2021	J	`jnl`	A 77.1-dB-SNDR 6.25-MHz-BW Pipeline SAR ADC With Enhanced Interstage Gain Error Shaping and Quantization Noise Shaping. IEEE J. Solid State Circuits Chen-Kai Hsu, Xiyuan Tang, Jiaxin Liu, Rui Xu, Wenda Zhao, Abhishek Mukherjee, Timothy R. Andeen, Nan Sun
2021	—	`conf`	A 79dB-SNDR 167dB-FoM Bandpass ΔΣ ADC Combining N-Path Filter with Noise-Shaping SAR. ISSCC Linxiao Shen, Zijie Gao, Xiangxing Yang, Wei Shi, Nan Sun
2021	J	`jnl`	A 90-dB-SNDR Calibration-Free Fully Passive Noise-Shaping SAR ADC With 4× Passive Gain and Second-Order DAC Mismatch Error Shaping. IEEE J. Solid State Circuits Jiaxin Liu, Xing Wang, Zijie Gao, Mingtao Zhan, Xiyuan Tang, Chen-Kai Hsu, Nan Sun
2021	J	`jnl`	A Fully Dynamic Low-Power Wideband Time-Interleaved Noise-Shaping SAR ADC. IEEE J. Solid State Circuits Haoyu Zhuang, Jiaxin Liu, He Tang, Xizhu Peng, Nan Sun
2021	—	`conf`	An 81.5dB-DR 1.25MHz-BW VCO-Based CT ΔΣ ADC with Double-PFD Quantizer. CICC Yi Zhong, Xiyuan Tang, Jiaxin Liu, Wenda Zhao, Shaolan Li, Nan Sun
2021	—	`conf`	An In-Memory-Computing Charge-Domain Ternary CNN Classifier. CICC Xiangxing Yang, Keren Zhu, Xiyuan Tang, Meizhi Wang, Mingtao Zhan, Nanshu Lu, Jaydeep P. Kulkarni, David Z. Pan, Yongpan Liu, Nan Sun
2021	A*	`conf`	DNN-Opt: An RL Inspired Optimization for Analog Circuit Sizing using Deep Neural Networks. DAC Ahmet Faruk Budak, Prateek Bhansali, Bo Liu, Nan Sun, David Z. Pan, Chandramouli V. Kashyap
2021	J	`jnl`	DNN-Opt: An RL Inspired Optimization for Analog Circuit Sizing using Deep Neural Networks. CoRR Ahmet Faruk Budak, Prateek Bhansali, Bo Liu, Nan Sun, David Z. Pan, Chandramouli V. Kashyap
2021	J	`jnl`	High-Precision ADC Testing With Relaxed Reference Voltage Stationarity. IEEE Trans. Instrum. Meas. Vivek Varier, Nan Sun
2021	—	`conf`	MAGICAL 1.0: An Open-Source Fully-Automated AMS Layout Synthesis Framework Verified With a 40-nm 1GS/s Δ∑ ADC. CICC Hao Chen, Mingjie Liu, Xiyuan Tang, Keren Zhu, Abhishek Mukherjee, Nan Sun, David Z. Pan
2021	J	`jnl`	MAGICAL: An Open- Source Fully Automated Analog IC Layout System from Netlist to GDSII. IEEE Des. Test Hao Chen, Mingjie Liu, Biying Xu, Keren Zhu, Xiyuan Tang, Shaolan Li, Yibo Lin, Nan Sun, David Z. Pan
2021	A	`conf`	OpenSAR: An Open Source Automated End-to-end SAR ADC Compiler. ICCAD Mingjie Liu, Xiyuan Tang, Keren Zhu, Hao Chen, Nan Sun, David Z. Pan
2021	J	`jnl`	Portable CMOS NMR System With 50-kHz IF, 10-μs Dead Time, and Frequency Tracking. IEEE Trans. Circuits Syst. I Regul. Pap. Sungjin Hong, Nan Sun
2021	A*	`conf`	Universal Symmetry Constraint Extraction for Analog and Mixed-Signal Circuits with Graph Neural Networks. DAC Hao Chen, Keren Zhu, Mingjie Liu, Xiyuan Tang, Nan Sun, David Z. Pan
2020	—	`conf`	16.5 A 13b 0.005mm ISSCC Jiaxin Liu, Xiyuan Tang, Wenda Zhao, Linxiao Shen, Nan Sun
2020	—	`conf`	9.3 A 40kHz-BW 90dB-SNDR Noise-Shaping SAR with 4× Passive Gain and 2 ISSCC Jiaxin Liu, Xing Wang, Zijie Gao, Mingtao Zhan, Xiyuan Tang, Nan Sun
2020	—	`conf`	9.5 A 13.5b-ENOB Second-Order Noise-Shaping SAR with PVT-Robust Closed-Loop Dynamic Amplifier. ISSCC Xiyuan Tang, Xiangxing Yang, Wenda Zhao, Chen-Kai Hsu, Jiaxin Liu, Linxiao Shen, Abhishek Mukherjee, Wei Shi, David Z. Pan, Nan Sun
2020	J	`jnl`	A 0.025-mm IEEE J. Solid State Circuits Wenda Zhao, Shaolan Li, Biying Xu, Xiangxing Yang, Xiyuan Tang, Linxiao Shen, Nanshu Lu, David Z. Pan, Nan Sun
2020	—	`conf`	A 10-Bit 100-MS/s SAR ADC with Always-on Reference Ripple Cancellation. VLSI Circuits Xiyuan Tang, Yi Shen, Xin Xin, Shubin Liu, Jueping Cai, Zhangming Zhu, Nan Sun
2020	J	`jnl`	A 10-bit 120-MS/s SAR ADC With Reference Ripple Cancellation Technique. IEEE J. Solid State Circuits Yi Shen, Xiyuan Tang, Linxiao Shen, Wenda Zhao, Xin Xin, Shubin Liu, Zhangming Zhu, Visvesh Sathe, Nan Sun
2020	J	`jnl`	A 13-bit 0.005-mm IEEE J. Solid State Circuits Jiaxin Liu, Xiyuan Tang, Wenda Zhao, Linxiao Shen, Nan Sun
2020	J	`jnl`	A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier. IEEE J. Solid State Circuits Xiyuan Tang, Xiangxing Yang, Wenda Zhao, Chen-Kai Hsu, Jiaxin Liu, Linxiao Shen, Abhishek Mukherjee, Wei Shi, Shaolan Li, David Z. Pan, Nan Sun
2020	J	`jnl`	A 7-bit 900-MS/s 2-Then-3-bit/cycle SAR ADC With Background Offset Calibration. IEEE J. Solid State Circuits Dengquan Li, Zhangming Zhu, Jiaxin Liu, Haoyu Zhuang, Yintang Yang, Nan Sun
2020	—	`conf`	A 77.1-dB 6.25-MHz-BW Pipeline SAR ADC with Enhanced Interstage Gain Error Shaping and Quantization Error Shaping. CICC Chen-Kai Hsu, Xiyuan Tang, Wenda Zhao, Rui Xu, Abhishek Mukherjee, Timothy R. Andeen, Nan Sun
2020	J	`jnl`	A Fractional- IEEE J. Solid State Circuits Yanlong Zhang, Arindam Sanyal, Xueyi Yu, Xing Quan, Kailin Wen, Xiyuan Tang, Gang Jin, Li Geng, Nan Sun
2020	—	`conf`	A Fully-Dynamic Time-Interleaved Noise-Shaping SAR ADC Based on CIFF Architecture. CICC Haoyu Zhuang, Jiaxin Liu, Nan Sun
2020	J	`jnl`	A New Method Based on Coding Sequence Density to Cluster Bacteria. J. Comput. Biol. Nan Sun, Rui Dong, Shaojun Pei, Changchuan Yin, Stephen S.-T. Yau
2020	J	`jnl`	A Pipeline SAR ADC With Second-Order Interstage Gain Error Shaping. IEEE J. Solid State Circuits Chen-Kai Hsu, Timothy R. Andeen, Nan Sun
2020	—	`conf`	A Portable NMR System with 50-kHz IF, 10-us Dead Time, and Frequency Tracking. VLSI Circuits Sungjin Hong, Nan Sun
2020	—	`conf`	A Power-Efficient 13-Tap FIR filter and an IIR Filter Embedded in a 10-bit SAR ADC. A-SSCC Xin Xin, Linxiao Shen, Xiyuan Tang, Yi Shen, Jueping Cai, Nan Sun
2020	—	`conf`	A SAR ADC with Reduced kT/C Noise by Decoupling Noise PSD and BW. VLSI Circuits Zhelu Li, Arnab Dutta, Abhishek Mukherjee, Xiyuan Tang, Linxiao Shen, Lenian He, Nan Sun
2020	J	`jnl`	A Second-Order Purely VCO-Based CT ΔΣ ADC Using a Modified DPLL Structure in 40-nm CMOS. IEEE J. Solid State Circuits Yi Zhong, Shaolan Li, Xiyuan Tang, Linxiao Shen, Wenda Zhao, Siliang Wu, Nan Sun
2020	J	`jnl`	A Strong Subthreshold Current Array PUF Resilient to Machine Learning Attacks. IEEE Trans. Circuits Syst. I Regul. Pap. Haoyu Zhuang, Xiaodan Xi, Nan Sun, Michael Orshansky
2020	—	`conf`	An Always-on 4× Compressive VGA CMOS Imager with 51pJ/Pixel and >32dB PSNR. VLSI Circuits Wenda Zhao, Chanmin Park, Injun Park, Nan Sun, Youngcheol Chae
2020	J	`jnl`	An Energy-Efficient Comparator With Dynamic Floating Inverter Amplifier. IEEE J. Solid State Circuits Xiyuan Tang, Linxiao Shen, Begum Kasap, Xiangxing Yang, Wei Shi, Abhishek Mukherjee, David Z. Pan, Nan Sun
2020	C	`conf`	An Energy-Efficient Flexible Capacitive Pressure Sensing System. ISCAS Yuxuan Huang, Qinghang Zhao, Xiyuan Tang, Fang Su, Nan Sun, Huazhong Yang, Yongpan Liu
2020	J	`jnl`	An Energy-Efficient Time-Domain Incremental Zoom Capacitance-to-Digital Converter. IEEE J. Solid State Circuits Xiyuan Tang, Shaolan Li, Xiangxing Yang, Linxiao Shen, Wenda Zhao, Randall P. Williams, Jiaxin Liu, Zhichao Tan, Neal A. Hall, David Z. Pan, Nan Sun
2020	J	`jnl`	An OTA-Less Second-Order VCO-Based CT $\Delta\Sigma$ Modulator Using an Inherent Passive Integrator and Capacitive Feedback. IEEE J. Solid State Circuits Shaolan Li, David Z. Pan, Nan Sun
2020	A*	`conf`	Closing the Design Loop: Bayesian Optimization Assisted Hierarchical Analog Layout Synthesis. DAC Mingjie Liu, Keren Zhu, Xiyuan Tang, Biying Xu, Wei Shi, Nan Sun, David Z. Pan
2020	A	`conf`	Effective Analog/Mixed-Signal Circuit Placement Considering System Signal Flow. ICCAD Keren Zhu, Hao Chen, Mingjie Liu, Xiyuan Tang, Nan Sun, David Z. Pan
2020	A*	`conf`	GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learning. DAC Hanrui Wang, Kuan Wang, Jiacheng Yang, Linxiao Shen, Nan Sun, Hae-Seung Lee, Song Han
2020	J	`jnl`	GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learning. CoRR Hanrui Wang, Kuan Wang, Jiacheng Yang, Linxiao Shen, Nan Sun, Hae-Seung Lee, Song Han
2020	J	`jnl`	Guest Editorial 2019 Custom Integrated Circuits Conference. IEEE J. Solid State Circuits Nan Sun, Qun Jane Gu
2020	—	`conf`	S ASP-DAC Mingjie Liu, Wuxi Li, Keren Zhu, Biying Xu, Yibo Lin, Linxiao Shen, Xiyuan Tang, Nan Sun, David Z. Pan
2020	A	`conf`	Toward Silicon-Proven Detailed Routing for Analog and Mixed-Signal Circuits. ICCAD Hao Chen, Keren Zhu, Mingjie Liu, Xiyuan Tang, Nan Sun, David Z. Pan
2020	A	`conf`	Towards Decrypting the Art of Analog Layout: Placement Quality Prediction via Transfer Learning. DATE Mingjie Liu, Keren Zhu, Jiaqi Gu, Linxiao Shen, Xiyuan Tang, Nan Sun, David Z. Pan
2019	—	`conf`	A 0.01mm ISSCC Linxiao Shen, Yi Shen, Xiyuan Tang, Chen-Kai Hsu, Wei Shi, Shaolan Li, Wenda Zhao, Abhishek Mukherjee, Nan Sun
2019	—	`conf`	A 0.025-mm CICC Shaolan Li, Wenda Zhao, Biying Xu, Xiangxing Yang, Xiyuan Tang, Linxiao Shen, Nanshu Lu, David Z. Pan, Nan Sun
2019	J	`jnl`	A 0.029-mm IEEE J. Solid State Circuits Jiaxin Liu, Shaolan Li, Wenjuan Guo, Guangjun Wen, Nan Sun
2019	—	`conf`	A 0.6-V Tail-Less Inverter Stacking Amplifier with 0.96 PEF. VLSI Circuits Linxiao Shen, Abhishek Mukherjee, Shaolan Li, Xiyuan Tang, Nanshu Lu, Nan Sun
2019	J	`jnl`	A 10-Bit 600-MS/s Time-Interleaved SAR ADC With Interpolation-Based Timing Skew Calibration. IEEE Trans. Circuits Syst. II Express Briefs Dengquan Li, Zhangming Zhu, Ruixue Ding, Maliang Liu, Yintang Yang, Nan Sun
2019	J	`jnl`	A 10-b 600-MS/s 2-Way Time-Interleaved SAR ADC With Mean Absolute Deviation-Based Background Timing-Skew Calibration. IEEE Trans. Circuits Syst. I Regul. Pap. Jeonggoo Song, Kareem Ragab, Xiyuan Tang, Nan Sun
2019	—	`conf`	A 10b 120MS/s SAR ADC with Reference Ripple Cancellation Technique. CICC Xiyuan Tang, Yi Shen, Linxiao Shen, Wenda Zhao, Zhangming Zhu, Visvesh Sathe, Nan Sun
2019	—	`conf`	A 16fJ/Conversion-Step Time-Domain Two-Step Capacitance-to-Digital Converter. ISSCC Xiyuan Tang, Shaolan Li, Linxiao Shen, Wenda Zhao, Xiangxing Yang, Randy Williams, Jiaxin Liu, Zhichao Tan, Neal A. Hall, Nan Sun
2019	—	`conf`	A 2.4-GHz ΔΣ Fractional-N Synthesizer with Space-Time Averaging for Noise Reduction. CICC Yanlong Zhang, Arindam Sanyal, Xing Quan, Kailin Wen, Xiyuan Tang, Gang Jin, Li Geng, Nan Sun
2019	—	`conf`	A 60-fJ/step 11-ENOB VCO-based CTDSM Synthesized from Digital Standard Cell Library. CICC Shaolan Li, Biying Xu, David Z. Pan, Nan Sun
2019	—	`conf`	A 75.8dB-SNDR Pipeline SAR ADC with 2 VLSI Circuits Chen-Kai Hsu, Nan Sun
2019	—	`conf`	A 7b 2.6mW 900MS/s Nonbinary 2-then-3b/cycle SAR ADC with Background Offset Calibration. CICC Dengquan Li, Jiaxin Liu, Haoyu Zhuang, Zhangming Zhu, Yintang Yang, Nan Sun
2019	J	`jnl`	A Second-Order Noise-Shaping SAR ADC With Passive Integrator and Tri-Level Voting. IEEE J. Solid State Circuits Haoyu Zhuang, Wenjuan Guo, Jiaxin Liu, He Tang, Zhangming Zhu, Long Chen, Nan Sun
2019	J	`jnl`	A Two-Step ADC With a Continuous-Time SAR-Based First Stage. IEEE J. Solid State Circuits Linxiao Shen, Nan Sun, Yi Shen, Zhelu Li, Wei Shi, Xiyuan Tang, Shaolan Li, Wenda Zhao, Mantian Zhang, Zhangming Zhu
2019	J	`jnl`	Advances in Voltage-Controlled-Oscillator-Based ΔΣ ADCs. IEICE Trans. Electron. Shaolan Li, Arindam Sanyal, Kyoungtae Lee, Yeonam Yoon, Xiyuan Tang, Yi Zhong, Kareem Ragab, Nan Sun
2019	—	`conf`	An Energy-Efficient Comparator with Dynamic Floating Inverter Pre-Amplifier. VLSI Circuits Xiyuan Tang, Begum Kasap, Linxiao Shen, Xiangxing Yang, Wei Shi, Nan Sun
2019	—	`conf`	Device Layer-Aware Analytical Placement for Analog Circuits. ISPD Biying Xu, Shaolan Li, Chak-Wa Pui, Derong Liu, Linxiao Shen, Yibo Lin, Nan Sun, David Z. Pan
2019	J	`jnl`	Error-Feedback Mismatch Error Shaping for High-Resolution Data Converters. IEEE Trans. Circuits Syst. I Regul. Pap. Jiaxin Liu, Chen-Kai Hsu, Xiyuan Tang, Shaolan Li, Guangjun Wen, Nan Sun
2019	A	`conf`	GeniusRoute: A New Analog Routing Paradigm Using Generative Neural Network Guidance. ICCAD Keren Zhu, Mingjie Liu, Yibo Lin, Biying Xu, Shaolan Li, Xiyuan Tang, Nan Sun, David Z. Pan
2019	A	`conf`	MAGICAL: Toward Fully Automated Analog IC Layout Leveraging Human and Machine Intelligence: Invited Paper. ICCAD Biying Xu, Keren Zhu, Mingjie Liu, Yibo Lin, Shaolan Li, Xiyuan Tang, Nan Sun, David Z. Pan
2019	A*	`conf`	WellGAN: Generative-Adversarial-Network-Guided Well Generation for Analog/Mixed-Signal Circuit Layout. DAC Biying Xu, Yibo Lin, Xiyuan Tang, Shaolan Li, Linxiao Shen, Nan Sun, David Z. Pan
2018	—	`conf`	A 0.029MM2 17-FJ/Conv.-Step CT $\Delta\Sigma$ ADC with 2 VLSI Circuits Jiaxin Liu, Shaolan Li, Wenjuan Guo, Guangjun Wen, Nan Sun
2018	J	`jnl`	A 1-V 0.25-µW Inverter Stacking Amplifier With 1.07 Noise Efficiency Factor. IEEE J. Solid State Circuits Linxiao Shen, Nanshu Lu, Nan Sun
2018	—	`conf`	A 13-ENOB 2 ISSCC Shaolan Li, Bo Qiao, Miguel Gandara, Nan Sun
2018	J	`jnl`	A 13-ENOB Second-Order Noise-Shaping SAR ADC Realizing Optimized NTF Zeros Using the Error-Feedback Structure. IEEE J. Solid State Circuits Shaolan Li, Bo Qiao, Miguel Gandara, David Z. Pan, Nan Sun
2018	—	`conf`	A Second-Order Purely VCO-Based CT Δ∑ ADC Using a Modified DPLL in 40-nm CMOS. A-SSCC Yi Zhong, Shaolan Li, Arindam Sanyal, Xiyuan Tang, Linxiao Shen, Siliang Wu, Nan Sun
2018	C	`conf`	Low-power Scaling-friendly Ring Oscillator based ΔΣ ADC. ISCAS Arindam Sanyal, Shaolan Li, Nan Sun
2017	J	`jnl`	A 0.7-V 0.6-µW 100-kS/s Low-Power SAR ADC With Statistical Estimation-Based Noise Reduction. IEEE J. Solid State Circuits Long Chen, Xiyuan Tang, Arindam Sanyal, Yeonam Yoon, Jie Cong, Nan Sun
2017	J	`jnl`	A 0.95-mW 6-b 700-MS/s Single-Channel Loop-Unrolled SAR ADC in 40-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs Long Chen, Kareem Ragab, Xiyuan Tang, Jeonggoo Song, Arindam Sanyal, Nan Sun
2017	—	`conf`	A 1.5fJ/conv-step 10b 100kS/s SAR ADC with gain-boosted dynamic comparator. A-SSCC Xiyuan Tang, Long Chen, Jeonggoo Song, Nan Sun
2017	—	`conf`	A 10-b 2b/cycle 300MS/s SAR ADC with a single differential DAC in 40nm CMOS. CICC Jeonggoo Song, Xiyuan Tang, Nan Sun
2017	J	`jnl`	A 10-b 800-MS/s Time-Interleaved SAR ADC With Fast Variance-Based Timing-Skew Calibration. IEEE J. Solid State Circuits Jeonggoo Song, Kareem Ragab, Xiyuan Tang, Nan Sun
2017	J	`jnl`	A 12-b ENOB 2.5-MHz BW VCO-Based 0-1 MASH ADC With Direct Digital Background Calibration. IEEE J. Solid State Circuits Kareem Ragab, Nan Sun
2017	—	`conf`	A 172dB-FoM pipelined SAR ADC using a regenerative amplifier with self-timed gain control and mixed-signal background calibration. A-SSCC Miguel Gandara, Paridhi Gulati, Nan Sun
2017	J	`jnl`	A 174.3-dB FoM VCO-Based CT ΔΣ Modulator With a Fully-Digital Phase Extended Quantizer and Tri-Level Resistor DAC in 130-nm CMOS. IEEE J. Solid State Circuits Shaolan Li, Abhishek Mukherjee, Nan Sun
2017	A*	`conf`	A Scaling Compatible, Synthesis Friendly VCO-based Delta-sigma ADC Design and Synthesis Methodology. DAC Biying Xu, Shaolan Li, Nan Sun, David Z. Pan
2017	—	`conf`	A pipelined SAR ADC reusing the comparator as residue amplifier. CICC Miguel Gandara, Wenjuan Guo, Xiyuan Tang, Long Chen, Yeonam Yoon, Nan Sun
2017	J	`jnl`	An Energy-Efficient Hybrid SAR-VCO ΔΣ Capacitance-to-Digital Converter in 40-nm CMOS. IEEE J. Solid State Circuits Arindam Sanyal, Nan Sun
2017	—	`conf`	Hierarchical and Analytical Placement Techniques for High-Performance Analog Circuits. ISPD Biying Xu, Shaolan Li, Xiaoqing Xu, Nan Sun, David Z. Pan
2017	—	`conf`	Integrated CMOS spectrometer for multi-dimensional NMR spectroscopy. MWSCAS Dongwan Ha, Nan Sun, Jeffrey Paulsen, Yi-Qiao Song, Yiqiao Tang, Sungjin Hong, Donhee Ham
2017	—	`conf`	NFC-enabled, tattoo-like stretchable biosensor manufactured by "cut-and-paste" method. EMBC Hyoyoung Jeong, Taewoo Ha, Irene Kuang, Linxiao Shen, Zhaohe Dai, Nan Sun, Nanshu Lu
2016	—	`conf`	A 1.4mW 8b 350MS/s loop-unrolled SAR ADC with background offset calibration in 40nm CMOS. ESSCIRC Kareem Ragab, Nan Sun
2016	—	`conf`	A 10-b 750µW 200MS/s fully dynamic single-channel SAR ADC in 40nm CMOS. ESSCIRC Xiyuan Tang, Long Chen, Jeonggoo Song, Nan Sun
2016	—	`conf`	A 10-b 800MS/s time-interleaved SAR ADC with fast timing-skew calibration. A-SSCC Jeonggoo Song, Kareem Ragab, Xiyuan Tang, Nan Sun
2016	—	`conf`	A 174.3dB FoM VCO-based CT ΔΣ modulator with a fully digital phase extended quantizer and tri-level resistor DAC in 130nm CMOS. ESSCIRC Shaolan Li, Nan Sun
2016	—	`conf`	A 18.5-fJ/step VCO-based 0-1 MASH ΔΣ ADC with digital background calibration. VLSI Circuits Arindam Sanyal, Nan Sun
2016	—	`conf`	A 55fJ/conv-step hybrid SAR-VCO ΔΣ capacitance-to-digital converter in 40nm CMOS. ESSCIRC Arindam Sanyal, Nan Sun
2016	B	`conf`	A surrogate model assisted evolutionary algorithm for computationally expensive design optimization problems with discrete variables. CEC Bo Liu, Nan Sun, Qingfu Zhang, Vic Grout, Georges G. E. Gielen
2016	C	`conf`	Comparator common-mode variation effects analysis and its application in SAR ADCs. ISCAS Long Chen, Arindam Sanyal, Ji Ma, Xiyuan Tang, Nan Sun
2015	—	`conf`	A 0.04-mm CICC Yeonam Yoon, Kyoungtae Lee, Sungjin Hong, Xiyuan Tang, Long Chen, Nan Sun
2015	—	`conf`	A 10.5-b ENOB 645 nW 100kS/s SAR ADC with statistical estimation based noise reduction. CICC Long Chen, Xiyuan Tang, Arindam Sanyal, Yeonam Yoon, Jie Cong, Nan Sun
2015	—	`conf`	A 12b ENOB, 2.5MHz-BW, 4.8mW VCO-based 0-1 MASH ADC with direct digital background nonlinearity calibration. CICC Kareem Ragab, Nan Sun
2015	J	`jnl`	A Novel Hybrid Radix-3/Radix-2 SAR ADC With Fast Convergence and Low Hardware Complexity. IEEE Trans. Circuits Syst. II Express Briefs Manzur Rahman, Arindam Sanyal, Nan Sun
2015	J	`jnl`	Digital Background Calibration for Pipelined ADCs Based on Comparator Decision Time Quantization. IEEE Trans. Circuits Syst. II Express Briefs Kareem Ragab, Long Chen, Arindam Sanyal, Nan Sun
2015	J	`jnl`	Dynamic Element Matching Techniques for Static and Dynamic Errors in Continuous-Time Multi-Bit ΔΣ Modulators. IEEE J. Emerg. Sel. Topics Circuits Syst. Arindam Sanyal, Nan Sun
2015	J	`jnl`	Dynamic Element Matching With Signal-Independent Element Transition Rates for Multibit ΔΣ Modulators. IEEE Trans. Circuits Syst. I Regul. Pap. Arindam Sanyal, Long Chen, Nan Sun
2014	—	`conf`	A 24-µW 11-bit 1-MS/s SAR ADC with a bidirectional single-side switching technique. ESSCIRC Long Chen, Arindam Sanyal, Ji Ma, Nan Sun
2014	J	`jnl`	A Thermometer-Like Mismatch Shaping Technique With Minimum Element Transition Activity for Multibit ΔΣ DACs. IEEE Trans. Circuits Syst. II Express Briefs Arindam Sanyal, Peijun Wang, Nan Sun
2014	—	`conf`	A hybrid SAR-VCO ΔΣ ADC with first-order noise shaping. CICC Arindam Sanyal, Kareem Ragab, Long Chen, T. R. Viswanathan, Shouli Yan, Nan Sun
2014	C	`conf`	A low frequency-dependence, energy-efficient switching technique for bottom-plate sampled SAR ADC. ISCAS Arindam Sanyal, Nan Sun
2014	C	`conf`	Algorithm and implementation of digital calibration of fast converging Radix-3 SAR ADC. ISCAS Manzur Rahman, Long Chen, Nan Sun
2014	J	`jnl`	An Energy-Efficient Low Frequency-Dependence Switching Technique for SAR ADCs. IEEE Trans. Circuits Syst. II Express Briefs Arindam Sanyal, Nan Sun
2014	C	`conf`	An enhanced ISI shaping technique for multi-bit ΔΣ DACs. ISCAS Arindam Sanyal, Nan Sun
2014	C	`conf`	Capacitor mismatch calibration for SAR ADCs based on comparator metastability detection. ISCAS Long Chen, Ji Ma, Nan Sun
2013	—	`conf`	A fast radix-3 SAR analog-to-digital converter. MWSCAS Long Chen, Manzur Rahman, Sha Liu, Nan Sun
2013	C	`conf`	A single SAR ADC converting multi-channel sparse signals. ISCAS Wenjuan Guo, Youngchun Kim, Arindam Sanyal, Ahmed H. Tewfik, Nan Sun
2013	—	`conf`	A very high energy-efficiency switching technique for SAR ADCs. MWSCAS Arindam Sanyal, Nan Sun
2013	J	`jnl`	Thermal Noise Analysis of a Programmable-Gain Switched-Capacitor Amplifier With Input Offset Cancellation. IEEE Trans. Circuits Syst. II Express Briefs Kareem Ragab, Mücahit Kozak, Nan Sun
2012	C	`conf`	A simple and efficient dithering method for vector quantizer based mismatch-shaped ΔΣ DACs. ISCAS Arindam Sanyal, Nan Sun