Nan Qi - RankMe

80 papers C 6Journal 24Unranked 50

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A 10 000-Inference/s Bio-Inspired Spiking Vision Chip Based on an End-to-End SNN Embedding Image Signal Enhancement. IEEE J. Solid State Circuits Xu Yang, Fuming Lei, Na Tian, Cong Shi, Zhe Wang, Shuangming Yu, Runjiang Dou, Peng Feng, Nan Qi, Zhongming Wei, Jian Liu, Kaiyou Wang, Nanjian Wu, Liyuan Liu
2025	—	`conf`	19.8 A 0.65V-VDD 10.4-to-11.8GHz Fractional-N Sampling PLL Achieving 73.8fsrms Jitter, -271.5dB FoMN, and -61 dBc in-Band Fractional Spur in 40nm CMOS. ISSCC Xinyu Shen, Zhao Zhang, Yixi Li, Junjie Chen, Xiangjian Kong, Nan Qi, Jian Liu, Nanjian Wu, Liyuan Liu
2025	J	`jnl`	A 2 pA/√Hz Input-Referred Noise TIA in 180-nm CMOS With 2.5 GHz Bandwidth for Optical Receiver. IEEE Solid State Circuits Lett. Yihao Yang, Dan Li, Nan Qi, Binhao Wang
2025	—	`conf`	A 22.4-25.6GHz Ping-Pong Sub-Sampling PLL Featuring Unified Supply Voltage and Balanced 2 CICC Yunbo Huang, Zunsong Yang, Hongyu Ren, Rui Paulo Martins, Yan Lu, Nan Sun, Nan Qi, Yong Chen
2025	—	`conf`	A 4λ×128Gb/s PAM-4 Si-Photonic Transmitter with Micro-Ring Modulator and Co-designed Linear Driver for Chiplet Optical I/O. OFC Siyuan Ma, Yingjie Ma, Chaoyang Dai, Sikai Chen, Qianli Ma, Yihan Chen, Haoran Yin, Yujun Xie, Guike Li, Jian Liu, Ming Li, Liyuan Liu, Nan Qi
2025	J	`jnl`	A 56-Gb/s, 6.3-pJ/bit PAM-4 DFB Laser Driver Incorporating Asymmetric Equalization and Integrated CDR in 28 nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. Yang Min, Nan Qi, Yihan Chen, Yi Zhang, Minye Zhu, Guike Li, Yonghui Lin, Huiyao Peng, Mo Guang, Kaiwen Long, Zhao Zhang, Jian Liu, Nanjian Wu, Jingbo Shi, Yong Chen, Frank F. Shi, Liyuan Liu
2025	J	`jnl`	A Monolithically Integrated DWDM Si-Photonics Transceiver for Chiplet Optical I/O. IEEE J. Solid State Circuits Nan Qi, Qianli Ma, Ang Li, Minye Zhu, Ruoyu Wu, Yongliang Xiong, Yingjie Ma, Haoran Yin, Han Liu, Menghan Yang, Daofa Wang, Peng Wang, Yang Qu, Yujun Xie, Guike Li, Liyuan Liu, Ming Li
2025	J	`jnl`	A Six-Phase Harmonic-Rejection Digital Transmitter. IEEE J. Solid State Circuits Jiaxiang Li, Zimu Li, Yun Yin, Changgu Yan, Nan Qi, Ming Liu, Hongtao Xu
2024	—	`conf`	A 0.144 mm CICC Xinyu Shen, Zhao Zhang, Yong Chen, Yixi Li, Yidan Zhang, Guike Li, Nan Qi, Jian Liu, Nanjian Wu, Liyuan Liu
2024	—	`conf`	A 13.75-14.75-GHz 32.1-fsRMS Jitter -100.6-dBc Reference Spur -261.4-dB FoM Sub-Sampling PLL Using a KPD-Doubled Isolated Sub-Sampling Phase Detector for Reliable Spur-Jitter-Joint Optimization. A-SSCC Yiqing Xu, Yixi Li, Zhao Zhang, Nan Qi, Jian Liu, Nanjian Wu, Liyuan Liu
2024	—	`conf`	A 200Gb/s, 3.5pJ/bit Monolithically Integrated WDM SiPhotonic Transceiver for Chiplet Optical I/O. A-SSCC Qianli Ma, Ang Li, Yongliang Xiong, Yingjie Ma, Haoran Yin, Han Liu, Minye Zhu, Menghan Yang, Ye Jin, Daofa Wang, Peng Wang, Yang Qu, Yujun Xie, Guike Li, Liyuan Liu, Nan Qi, Ming Li
2024	—	`conf`	A 2λ×100 Gb/s Optical Receiver with Si-Photonic Micro-Ring Resonator and Photo-Detector for DWDM Optical-IO. CICC Sikai Chen, Jintao Xue, Yihan Chen, Yuean Gu, Haoran Yin, Shenlei Bao, Guike Li, Binhao Wang, Nan Qi
2024	C	`conf`	A 32Gb/s NRZ Low-Bias DFB Driver with Frequency Boosting for High Efficiency Data Transmission. ISCAS Yang Min, Yi Zhang, Tao Yang, Leliang Li, Guike Li, Zhao Zhang, Jian Liu, Nanjian Wu, Yonghui Lin, Huiyao Peng, Jingbo Shi, Nan Qi
2024	J	`jnl`	A 4×112 Gb/s PAM-4 Silicon-Photonic Transmitter and Receiver Chipsets for Linear-Drive Co-Packaged Optics. IEEE J. Solid State Circuits Han Liu, Zhihan Zhang, Ye Liu, Daigao Chen, Donglai Lu, Jian He, Guike Li, Min Liu, Ziyue Dang, Xi Xiao, Nan Qi
2024	—	`conf`	A 64-GBaud 64-QAM Optical Coherent Transmitter with Monolithically Integrated Driver and I/Q Modulator in 45-nm SOI CMOS. ICTA Yizhou Xu, Ruogu Deng, Jingbo Wang, Han Liu, Zhihan Zhang, Yihao Yang, Guike Li, Binhao Wang, Nan Qi, Liyuan Liu
2024	—	`conf`	A 64Gb/s Si-Photonic Micro-Ring Resonator Transceiver with Co-designed CMOS Driver and TIA for WDM Optical-IO. BCICTS Qianli Ma, Sikai Chen, Jintao Xue, Yingjie Ma, Yuean Gu, Chao Cheng, Yihan Chen, Haoran Yin, Guike Li, Zhao Zhang, Nanjian Wu, Ke Li, Lei Wang, Ming Li, Chao Xiang, Binhao Wang, Nan Qi, Liyuan Liu
2024	J	`jnl`	A Bio-Inspired Spiking Vision Chip Based on SPAD Imaging and Direct Spike Computing for Versatile Edge Vision. IEEE J. Solid State Circuits Xu Yang, Chunhe Yao, Lei Kang, Qian Luo, Nan Qi, Runjiang Dou, Shuangming Yu, Peng Feng, Zhongming Wei, Jian Liu, Kaiyou Wang, Nanjian Wu, Liyuan Liu
2023	—	`conf`	A $\boldsymbol{4} \times \boldsymbol{112}-\mathbf{Gb}/\mathbf{s}$ PAM-4 Silicon-Photonic Transceiver Front-End for Linear-Drive Co-Packaged Optics. A-SSCC Han Liu, Nan Qi, Donglai Lu, Zizheng Dong, Zhihan Zhang, Jian He, Guike Li, Leliang Li, Ye Liu, Ziyue Dang, Daigao Chen, Zhao Zhang, Jian Liu, Nanjian Wu, Xi Xiao, Liyuan Liu
2023	—	`conf`	A 0.0035-mm ESSCIRC Zhaoyu Zhang, Zhao Zhang, Yong Chen, Guoqing Wang, Xinyu Shen, Nan Qi, Guike Li, Shuangming Yu, Jian Liu, Nanjian Wu, Liyuan Liu
2023	—	`conf`	A 12.75-to-16-GHz Spur-Jitter-Joint-Optimization SS-PLL Achieving -94.55-dBc Reference Spur, 31.9-fs Integrated Jitter and -260.1-dB FoM. A-SSCC Yixi Li, Zhao Zhang, Yong Chen, Xinyu Shen, Nan Qi, Jian Liu, Nanjian Wu, Liyuan Liu
2023	—	`conf`	A 4-12.1-GHz Fractional-N Ring Sampling PLL Based on Adaptively-Biased PD-Merged DTC Achieving -37.6± 0.9-dBc Integrated Phase Noise, 261.9-fs RMS Jitter, and -240.6-dB FoM. ESSCIRC Xinyu Shen, Zhao Zhang, Guike Li, Yong Chen, Nan Qi, Jian Liu, Nanjian Wu, Liyuan Liu
2023	—	`conf`	A 400-Gb/s 64-QAM Optical Receiver with Monolithically Integrated TIA and Balanced-PD in 45-nm SOI CMOS. ICTA Yongliang Xiong, Yihao Yang, Qianli Ma, Yangming Ren, Leliang Li, Guike Li, Jian Liu, Yingtao Li, Binhao Wang, Nan Qi, Liyuan Liu
2023	J	`jnl`	A 50Gb/s CMOS Optical Receiver With Si-Photonics PD for High-Speed Low-Latency Chiplet I/O. IEEE Trans. Circuits Syst. I Regul. Pap. Sikai Chen, Mingyang You, Yunqi Yang, Ye Jin, Ziyi Lin, Yihong Li, Leliang Li, Guike Li, Yujun Xie, Zhao Zhang, Binhao Wang, Ningfeng Tang, Faju Liu, Zheyu Fang, Jian Liu, Nanjian Wu, Yong Chen, Liyuan Liu, Ninghua Zhu, Ming Li, Nan Qi
2023	—	`conf`	A 64-Gb/s Reference-Less PAM4 CDR with Asymmetrical Linear Phase Detector Soring 231.5-fsrms Clock Jitter and 0.21-pJ/bit Energy Efficiency in 40-nm CMOS. VLSI Technology and Circuits Zhao Zhang, Zhaoyu Zhang, Yong Chen, Nan Qi, Jian Liu, Nanjian Wu, Liyuan Liu
2023	—	`conf`	A O.4V-VDD 2.25-to-2.75GHz ULV-SS-PLL Achieving 236.6fsrms Jitter, -253.8dB Jitter-Power FoM, and -76.1dBc Reference Spur. ISSCC Zhao Zhang, Xinyu Shen, Zhaoyu Zhang, Guike Li, Nan Qi, Jian Liu, Yong Chen, Nanjian Wu, Liyuan Liu
2023	—	`conf`	A Wideband Low-Noise Linear LiDAR Analog Front-End Achieving 1.6 GHz Bandwidth, $\boldsymbol{2.7}\ \mathbf{pA}/\mathbf{Hz}^{\boldsymbol{0.5}}$ Input Referred Noise, and 103 $\mathbf{dB}\mathbf{\Omega}$ Transimpedance Gain. A-SSCC Yidan Zhang, Zhao Zhang, Yiqing Xu, Xinyu Shen, Nan Qi, Nanjian Wu, Jian Liu, Liyuan Liu
2023	C	`conf`	An 800G Integrated Silicon-Photonic Transmitter based on 16-Channel Mach-Zehnder Modulator and Co-Designed 5.35pJ/bit CMOS Drivers. ISCAS Jingbo Shi, Han Liu, Tao Yang, Ming Jin, Haowen Shu, Fenghe Yang, Lei Shi, Yuansheng Tao, Jianrui Deng, Ruixuan Chen, Changhao Han, Jian Liu, Nanjian Wu, Nan Qi, Liyuan Liu
2022	—	`conf`	A 0.004-mm APCCAS Yixi Li, Xinyu Shen, Zhaoyu Zhang, Guike Li, Tao Yin, Nan Qi, Jian Liu, Nanjian Wu, Liyuan Liu, Yong Chen, Zhao Zhang
2022	—	`conf`	A 0.006-mm APCCAS Zhaoyu Zhang, Xinyu Shen, Yixi Li, Guike Li, Nan Qi, Jian Liu, Nanjian Wu, Liyuan Liu, Yong Chen, Zhao Zhang
2022	—	`conf`	A 224-Gb/s Inverter-Based TIA with Interleaved Active-Feedback and Distributed Peaking in 28-nm CMOS for Silicon Photonic Receivers. ICTA Sikai Chen, Jintao Xue, Leliang Li, Guike Li, Zhao Zhang, Jian Liu, Liyuan Liu, Binhao Wang, Yingtao Li, Nan Qi
2022	—	`conf`	A 28-Gb/s 13.8-mW Half-Rate Bang-Bang Clock and Data Recovery Circuit Using Return-to-Zero-Based Symmetrical Bang-Bang Phase Detector. NorCAS Xinyi Ge, Yong Chen, Lin Wang, Nan Qi, Pui-In Mak, Rui Paulo Martins
2022	—	`conf`	A 50-Gb/s NRZ Receiver Targeting Low-Latency Multi-Chip Module Optical I/O in 45-nm SOI CMOS. APCCAS Yihong Li, Sikai Chen, Yunqi Yang, Qianli Ma, Ming Zhong, Ziyi Lin, Leliang Li, Guike Li, Zhao Zhang, Liyuan Liu, Jian Liu, Nanjian Wu, Yong Chen, Qi Peng, Nan Qi
2022	J	`jnl`	A 50-Gb/s PAM-4 Silicon-Photonic Transmitter Incorporating Lumped-Segment MZM, Distributed CMOS Driver, and Integrated CDR. IEEE J. Solid State Circuits Qiwen Liao, Yuguang Zhang, Siyuan Ma, Lei Wang, Leliang Li, Guike Li, Zhao Zhang, Jian Liu, Nanjian Wu, Liyuan Liu, Yong Chen, Xi Xiao, Nan Qi
2022	J	`jnl`	A 56-Gb/s Reconfigurable Silicon-Photonics Transmitter Using High-Swing Distributed Driver and 2-Tap In-Segment Feed-Forward Equalizer in 65-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Jian He, Yuguang Zhang, Han Liu, Qiwen Liao, Zhao Zhang, Miaofeng Li, Fan Jiang, Jingbo Shi, Jian Liu, Nanjian Wu, Yong Chen, Patrick Yin Chiang, Ningmei Yu, Xi Xiao, Nan Qi
2022	—	`conf`	A 56Gb/s De-serializer with PAM-4 CDR for Chiplet Optical-I/O. ICTA Yunqi Yang, Ming Zhong, Qianli Ma, Ziyi Lin, Leliang Li, Guike Li, Liyuan Liu, Jian Liu, Nanjian Wu, Haikun Jia, Xinghui Liu, Nan Qi
2022	J	`jnl`	Design of a PAM-4 VCSEL-Based Transceiver Front-End for Beyond-400G Short-Reach Optical Interconnects. IEEE Trans. Circuits Syst. I Regul. Pap. Jian He, Donglai Lu, Haiyun Xue, Sikai Chen, Han Liu, Leliang Li, Guike Li, Zhao Zhang, Jian Liu, Liyuan Liu, Nanjian Wu, Ningmei Yu, Fengman Liu, Xi Xiao, Yong Chen, Nan Qi
2022	—	`conf`	Floorplanning and Power/Ground Network Design for A Programmable Vision Chip. ICTA Haozhe Xu, Siyuan Wei, Nan Qi, Peng Wu, Jian Liu, Nanjian Wu, Liyuan Liu, Shuangming Yu
2021	—	`conf`	100Gb/s PAM-4 VCSEL Driver and TIA for Short-Reach 400G-1.6T Optical Interconnects. APCCAS Donglai Lu, Jian He, Weizhong Li, Sikai Chen, Jian Liu, Nanjian Wu, Ningmei Yu, Liyuan Liu, Yong Chen, Xi Xiao, Nan Qi
2021	—	`conf`	A 32×32 Array Terahertz Sensor in 65-nm CMOS Technology. ICTA Tong Fang, Min Liu, Liyuan Liu, Ziteng Cai, Runjiang Dou, Peng Feng, Nan Qi, Zhao Zhang, Jian Liu, Nanjian Wu
2021	—	`conf`	A 4×25-Gb/s Serializer with Integrated CDR and 3-Tap FFE Driver for NIC Optical Interconnects. ICTA Ming Zhong, Qingwen Wang, Yong Chen, Jian Liu, Liyuan Liu, Xinghua Wang, Xiaoming Xiong, Nan Qi
2021	—	`conf`	A 4×25Gb/s De-Serializer with Baud-Rate Sampling CDR and Standing-Wave Clock Distribution for NIC Optical Interconnects. ICTA Mingyang You, Minjia Chen, Yihong Li, Guike Li, Jian Liu, Yong Chen, Yingtao Li, Nan Qi
2021	—	`conf`	A 50Gb/s High-Efficiency Si-Photonic Transmitter With Lump-Segmented MZM and Integrated PAM4 CDR. CICC Qiwen Liao, Miaofeng Li, Zhao Zhang, Jian Liu, Nanjian Wu, Xi Xiao, Nan Qi
2021	—	`conf`	A Fast-Transient Capacitor-Less Low-Dropout Regulator for Wideband Optical Transceivers. ICTA Han Liu, Guike Li, Jian Liu, Nanjian Wu, Liyuan Liu, Yingtao Li, Nan Qi
2020	C	`conf`	A 112-Gb/s PAM-4 Linear Optical Receiver in 130-nm SiGe BiCMOS. ISCAS Dan Li, Shengwei Gao, Yongjun Shi, Xiaoyan Gui, Nan Qi, Zhiyong Li, Quan Pan, Patrick Chiang, Li Geng
2020	—	`conf`	A 28GBaud High-Swing Linear Mach-Zehnder Modulators Driver for PAM-4 and Coherent Optical Communications. ICTA Kai Hao, Jian He, Leliang Li, Shuangming Yu, Liyuan Liu, Jian Liu, Ningmei Yu, Nanjian Wu, Nan Qi
2020	J	`jnl`	A 50-Gb/s PAM4 Si-Photonic Transmitter With Digital-Assisted Distributed Driver and Integrated CDR in 40-nm CMOS. IEEE J. Solid State Circuits Qiwen Liao, Nan Qi, Miaofeng Li, Shang Hu, Jian He, Bozhi Yin, Jingbo Shi, Jian Liu, Patrick Yin Chiang, Xi Xiao, Nanjian Wu
2020	C	`conf`	A 50Gb/s PAM-4 Optical Receiver with Si-Photonic PD and Linear TIA in 40nm CMOS. ISCAS Yang Liu, Nan Qi, Xiuli Xu, Weizhong Li, Lei Wang, Minjia Chen, Qixiang Cheng, Jingbo Shi, Liyuan Liu, Jian Liu, Xi Xiao, Nanjian Wu
2020	—	`conf`	A High-Speed Parallel FPGA Implementation of Harris Corner Detection. ICTA Hongtao Zhou, Runjiang Dou, Shuangming Yu, Nan Qi, Jian Liu, Nanjian Wu, Liyuan Liu
2019	J	`jnl`	0.1-5 GHz wideband ΔΣ fractional-N frequency synthesiser for software-defined radio application. IET Circuits Devices Syst. Zhao Zhang, Jincheng Yang, Liyuan Liu, Nan Qi, Peng Feng, Jian Liu, Nanjian Wu
2019	J	`jnl`	A 0.45-to-1.8 GHz synthesized injection-locked bang-bang phase locked loop with fine frequency tuning circuits. Sci. China Inf. Sci. Jincheng Yang, Zhao Zhang, Nan Qi, Liyuan Liu, Jian Liu, Nanjian Wu
2019	—	`conf`	A 50Gb/s PAM-4 Retimer-CDR + VCSEL Driver with Asymmetric Pulsed Pre-Emphasis Integrated into a Single CMOS Die. OFC Shang Hu, Tingyu Yao, Bozhi Yin, Chunyu Song, Lei Zhao, Juncheng Wang, Lei Wang, Rui Bai, Xin Wang, Tao Xia, Yi Peng, Binbin Yao, Yuan Li, Xuefeng Chen, Quan Pan, Nan Qi, Patrick Yin Chiang
2019	J	`jnl`	A Fully Integrated 25 Gb/s Low-Noise TIA+CDR Optical Receiver Designed in 40-nm-CMOS. IEEE Trans. Circuits Syst. II Express Briefs Juncheng Wang, Quan Pan, Yajie Qin, Xuefeng Chen, Shang Hu, Rui Bai, Xin Wang, Yaxin Cai, Tao Xia, Yuanxi Zhang, Jianxu Ma, Nan Qi, Patrick Yin Chiang
2019	J	`jnl`	An 18-23 GHz 57.4-fs RMS Jitter -253.5-dB FoM Sub-Harmonically Injection-Locked All-Digital PLL With Single-Ended Injection Technique and ILFD Aided Adaptive Injection Timing Alignment Technique. IEEE Trans. Circuits Syst. I Regul. Pap. Zhao Zhang, Jincheng Yang, Liyuan Liu, Nan Qi, Peng Feng, Jian Liu, Nanjian Wu
2019	—	`conf`	Design of High-Speed Drivers for 56Gb/s PAM4 Optical Communications in CMOS. ASICON Nan Qi, Nanjian Wu
2018	—	`conf`	A 3D-Integrated 56 Gb/s NRZ/PAM4 Reconfigurable Segmented Mach-Zehnder Modulator-Based Si-Photonics Transmitter. BCICTS Cheng Li, Kunzhi Yu, Jinsoo Rhim, Kehan Zhu, Nan Qi, Marco Fiorentino, Thierry Pinguet, Mark Peterson, Vishal Saxena, Samuel Palermo
2018	—	`conf`	A 50Gb/s-PAM4 CDR with On-Chip Eye Opening Monitor for Reference-Level and Clock-Sampling Adaptation. OFC Chang Liu, Bozhi Yin, Tingyu Yao, Nan Qi, Dan Li, Jingbo Shi, Juncheng Wang, Hu Shang, Rui Bai, Patrick Yin Chiang
2018	J	`jnl`	A 77-GHz Mixed-Mode FMCW Signal Generator Based on Bang-Bang Phase Detector. IEEE J. Solid State Circuits Jianfu Lin, Zheng Song, Nan Qi, Woogeun Rhee, Zhihua Wang, Baoyong Chi
2018	—	`conf`	A Fast Auto-Frequency Calibration Technique for Wideband PLL with Wide Reference Frequency Range. A-SSCC Zhao Zhang, Jincheng Yang, Liyuan Liu, Nan Qi, Peng Feng, Jian Liu, Nanjian Wu
2018	—	`conf`	A Fully-Integrated 25Gb/s Low-Noise TIA+CDR Optical Receiver designed in 40nm-CMOS. A-SSCC Juncheng Wang, Xuefeng Chen, Shang Hu, Yaxin Cai, Rui Bai, Xin Wang, Yuanxi Zhang, Shenglong Zhuo, Chang Liu, Bozhi Yin, Jianxu Ma, Hao Yan, Jiangao Xuan, Milton Lu, Tao Xia, Nan Qi, Patrick Yin Chiang
2018	J	`jnl`	Low-power 2.4 GHz ZigBee transceiver with inductor-less radio-frequency front-end for Internet of things applications. IET Circuits Devices Syst. Bing Xia, Nan Qi
2017	—	`conf`	A 51Gb/s, 320mW, PAM4 CDR with baud-rate sampling for high-speed optical interconnects. A-SSCC Nan Qi, Yuhang Kang, Qipeng Lin, Jianxu Ma, Jingbo Shi, Bozhi Yin, Chang Liu, Rui Bai, Shang Hu, Juncheng Wang, Jiangbing Du, Lin Ma, Zuyuan He, Ming Liu, Feng Zhang, Patrick Yin Chiang
2017	—	`conf`	A 77-GHz mixed-mode FMCW signal generator based on bang-bang phase detector. A-SSCC Jianfu Lin, Zheng Song, Nan Qi, Woogeun Rhee, Baoyong Chi
2017	—	`conf`	A low-power 2.4GHz ZigBee transceiver with inductor-less RF front-end for IoT applications. MWSCAS Bing Xia, Nan Qi, Liyuan Liu, Nanjian Wu
2016	—	`conf`	A 32Gb/s NRZ, 25GBaud/s PAM4 reconfigurable, Si-Photonic MZM transmitter in CMOS. OFC Nan Qi, Xi Xiao, Shang Hu, Miaofeng Li, Hao Li, Zhiyong Li, Patrick Chiang
2016	J	`jnl`	A 5-/20-MHz BW Reconfigurable Quadrature Bandpass CT ΔΣ ADC With AntiPole-Splitting Opamp and Digital I/Q Calibration. IEEE Trans. Very Large Scale Integr. Syst. Yang Xu, Zehong Zhang, Baoyong Chi, Nan Qi, Hualin Cai, Zhihua Wang
2015	—	`conf`	22.6 A 25Gb/s 4.4V-swing AC-coupled Si-photonic microring transmitter with 2-tap asymmetric FFE and dynamic thermal tuning in 65nm CMOS. ISSCC Hao Li, Zhe Xuan, Alex Titriku, Cheng Li, Kunzhi Yu, Binhao Wang, Ayman Shafik, Nan Qi, Yang Liu, Ran Ding, Tom Baehr Jones, Marco Fiorentino, Michael Hochberg, Samuel Palermo, Patrick Yin Chiang
2015	—	`conf`	A 20 μW dual-channel analog front-end in 65nm CMOS for portable ECG monitoring system. ASICON Shuo Li, Nan Qi, Vahid Behravan, Zhiliang Hong, Patrick Yin Chiang
2015	J	`jnl`	A 25 Gb/s, 4.4 V-Swing, AC-Coupled Ring Modulator-Based WDM Transmitter with Wavelength Stabilization in 65 nm CMOS. IEEE J. Solid State Circuits Hao Li, Zhe Xuan, Alex Titriku, Cheng Li, Kunzhi Yu, Binhao Wang, Ayman Shafik, Nan Qi, Yang Liu, Ran Ding, Tom Baehr Jones, Marco Fiorentino, Michael Hochberg, Samuel Palermo, Patrick Yin Chiang
2015	—	`conf`	A 25Gb/s, 520mW, 6.4Vpp Silicon-Photonic Mach-Zehnder Modulator with distributed driver in CMOS. OFC Nan Qi, Xianyao Li, Hao Li, Xi Xiao, Lei Wang, Zhiyong Li, Zhuo Gao, Yude Yu, Miki Moyal, Patrick Chiang
2014	—	`conf`	9.6 A 1.3mW 0.6V WBAN-compatible sub-sampling PSK receiver in 65nm CMOS. ISSCC Jiao Cheng, Nan Qi, Patrick Yin Chiang, Arun Natarajan
2014	J	`jnl`	A Low-Power, Low-Voltage WBAN-Compatible Sub-Sampling PSK Receiver in 65 nm CMOS. IEEE J. Solid State Circuits Jiao Cheng, Nan Qi, Patrick Yin Chiang, Arun Natarajan
2014	—	`conf`	A multi-mode reconfigurable analog baseband with I/Q calibration for GNSS receivers. ASP-DAC Zheng Song, Nan Qi, Baoyong Chi, Zhihua Wang
2013	—	`conf`	A 180nm fully-integrated dual-channel reconfigurable receiver for GNSS interoperations. ESSCIRC Nan Qi, Baoyong Chi, Yang Xu, Zhou Chen, Yang Xu, Jun Xie, Zheng Song, Zhihua Wang
2013	C	`conf`	A multi-mode complex bandpass filter with gm-assisted power optimization and I/Q calibration. ISCAS Nan Qi, Zheng Song, Baoyong Chi, Albert Z. Wang, Tianling Ren, Zhihua Wang
2013	—	`conf`	An asymmetric dual-channel reconfigurable receiver for GNSS in 180nm CMOS. CICC Nan Qi, Baoyong Chi, Yang Xu, Zhou Chen, Jun Xie, Yang Xu, Zheng Song, Zhihua Wang
2012	J	`jnl`	A Dual-Channel Compass/GPS/GLONASS/Galileo Reconfigurable GNSS Receiver in 65 nm CMOS With On-Chip I/Q Calibration. IEEE Trans. Circuits Syst. I Regul. Pap. Nan Qi, Yang Xu, Baoyong Chi, Yang Xu, Xiaobao Yu, Xing Zhang, Ni Xu, Patrick Chiang, Woogeun Rhee, Zhihua Wang
2012	C	`conf`	A hybrid approach to I/Q imbalance self-calibration in reconfigurable low-IF receivers. ISCAS Yang Xu, Nan Qi, Zhou Chen, Baoyong Chi, Zhihua Wang
2012	J	`jnl`	Power-Scalable, Complex Bandpass/Low-Pass Filter With I/Q Imbalance Calibration for a Multimode GNSS Receiver. IEEE Trans. Circuits Syst. II Express Briefs Yang Xu, Baoyong Chi, Xiaobao Yu, Nan Qi, Patrick Chiang, Zhihua Wang
2011	—	`conf`	A dual-channel GPS/Compass/Galileo/GLONASS reconfigurable GNSS receiver in 65nm CMOS. CICC Nan Qi, Yang Xu, Baoyong Chi, Yang Xu, Xiaobao Yu, Xing Zhang, Zhihua Wang
2009	J	`jnl`	A Wireless Capsule Endoscope System With Low-Power Controlling and Processing ASIC. IEEE Trans. Biomed. Circuits Syst. Xinkai Chen, Xiaoyu Zhang, Lingwei Zhang, Xiaowen Li, Nan Qi, Hanjun Jiang, Zhihua Wang