Nan-Chi Chou

18 papers A* 3A 7Journal 5Unranked 3
YearRankTypeTitle / Venue / Authors
2011 J jnl
Bus Matrix Synthesis Based on Steiner Graphs for Power Efficient System-on-Chip Communications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Renshen Wang, Yulei Zhang, Nan-Chi Chou, Evangeline F. Y. Young, Chung-Kuan Cheng, Ronald L. Graham
2009 A* conf
Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications.
DAC
Renshen Wang, Nan-Chi Chou, Bill Salefski, Chung-Kuan Cheng
2007 J jnl
Efficient Timing Analysis With Known False Paths Using Biclique Covering.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Michael D. Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris, Chung-Kuan Cheng
2005 — conf
A practical cut-based physical retiming algorithm for field programmable gate arrays.
ASP-DAC
Peter Suaris, Dongsheng Wang, Nan-Chi Chou
2005 A conf
Improving the efficiency of static timing analysis with false paths.
ICCAD
Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael D. Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris
2005 A conf
The effect of post-layout pin permutation on timing.
FPGA
Yuzheng Ding, Peter Suaris, Nan-Chi Chou
2005 — conf
Unified quadratic programming approach for mixed mode placement.
ISPD
Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Lung-Tien Liu, Peter Suaris
2004 A conf
Fast adders in modern FPGAs.
FPGA
Jianhua Liu, Michael Chang, Chung-Kuan Cheng, John F. MacDonald, Nan-Chi Chou, Peter Suaris
2004 A conf
Incremental physical resynthesis for timing optimization.
FPGA
Peter Suaris, Lung-Tien Liu, Yuzheng Ding, Nan-Chi Chou
2003 — conf
A Practical ASIC Methdology for Flexible Clock Tree Synthesis with Routing Blockages.
PATMOS
Dongsheng Wang, Peter Suaris, Nan-Chi Chou
2003 A conf
A physical retiming algorithm for field programmable gate arrays.
FPGA
Peter Suaris, Dongsheng Wang, Pei-Ning Guo, Nan-Chi Chou
2003 A* conf
An algebraic multigrid solver for analytical placement with layout based clustering.
DAC
Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Andrew B. Kahng, John F. MacDonald, Peter Suaris, Bo Yao, Zhengyong Zhu
1995 J jnl
Local ratio cut and set covering partitioning for huge logic emulation systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Nan-Chi Chou, Lung-Tien Liu, Chung-Kuan Cheng, Wei-Jin Dai, Rodney Lindelof
1995 J jnl
On general zero-skew clock net construction.
IEEE Trans. Very Large Scale Integr. Syst.
Nan-Chi Chou, Chung-Kuan Cheng
1994 J jnl
A multi-probe approach for MCM substrate testing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
So-Zen Yao, Nan-Chi Chou, Chung-Kuan Cheng, T. C. Hu
1994 A* conf
Circuit Partitioning for Huge Logic Emulation Systems.
DAC
Nan-Chi Chou, Lung-Tien Liu, Chung-Kuan Cheng, Wei-Jin Dai, Rodney Lindelof
1993 A conf
Performance-driven partitioning using retiming and replication.
ICCAD
Lung-Tien Liu, Minshine Shih, Nan-Chi Chou, Chung-Kuan Cheng, Walter H. Ku
1992 A conf
An optimal probe testing algorithm for the connectivity verification of MCM substrates.
ICCAD
So-Zen Yao, Nan-Chi Chou, Chung-Kuan Cheng, T. C. Hu