Nalesh Sivanandan

19 papers C 1Misc 3Journal 6Unranked 9
YearRankTypeTitle / Venue / Authors
2021 — conf
A Hardware-Software Co-design based Approach for Development of a Distributed DAQ System using FPGA.
VDAT
Abi K. Krishnan, M. H. Supriya, Nalesh Sivanandan
2021 — conf
Hardware Acceleration of SpMV Multiplier for Deep Learning.
VDAT
Mahesh Mahadurkar, Nalesh Sivanandan, S. Kala
2019 — conf
Efficient Hardware Acceleration of Convolutional Neural Networks.
SoCC
S. Kala, Babita R. Jose, Jimson Mathew, Nalesh Sivanandan
2019 J jnl
High-Performance CNN Accelerator on FPGA Using Unified Winograd-GEMM Architecture.
IEEE Trans. Very Large Scale Integr. Syst.
S. Kala, Babita R. Jose, Jimson Mathew, Nalesh Sivanandan
2019 J jnl
Radix-4
IET Comput. Digit. Tech.
S. Kala, Jimson Mathew, Babita R. Jose, Nalesh Sivanandan
2019 Misc conf
UniWiG: Unified Winograd-GEMM Architecture for Accelerating CNN on FPGAs.
VLSID
S. Kala, Jimson Mathew, Babita R. Jose, Nalesh Sivanandan
2018 J jnl
A Hardware Architecture for Radial Basis Function Neural Network Classifier.
IEEE Trans. Parallel Distributed Syst.
Mahnaz Mohammadi, Akhil Krishna, Nalesh Sivanandan, S. K. Nandy
2018 — conf
Design Space Exploration of Convolution Algorithms to Accelerate CNNs on FPGA.
ISED
S. Kala, Debdeep Paul, Babita R. Jose, Nalesh Sivanandan
2018 — conf
Two dimensional FFT architecture based on radix-4
DTIS
S. Kala, Nalesh Sivanandan, Babita R. Jose, Jimson Mathew, Marco Ottavi
2017 J jnl
Energy aware synthesis of application kernels through composition of data-paths on a CGRA.
Integr.
Nalesh Sivanandan, Kavitha T. Madhu, Saptarsi Das, S. K. Nandy, Ranjani Narayan
2016 Misc conf
RHyMe: REDEFINE Hyper Cell Multicore for Accelerating HPC Kernels.
VLSID
Saptarsi Das, Nalesh Sivanandan, Kavitha T. Madhu, Soumitra Kumar Nandy, Ranjani Narayan
2015 — conf
Compiling HPC Kernels for the REDEFINE CGRA.
HPCC/CSS/ICESS
Kavitha T. Madhu, Saptarsi Das, Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan
2015 — conf
Energy Aware Synthesis of Application Kernels Expressed in Functional Languages on a Coarse Grained Composable Reconfigurable Array.
iNIS
Nalesh Sivanandan, Kavitha T. Madhu, Saptarsi Das, S. K. Nandy, Ranjani Narayan
2015 Misc conf
Micro-architectural Enhancements in Distributed Memory CGRAs for LU and QR Factorizations.
VLSID
Farhad Merchant, Arka Maity, Mahesh Mahadurkar, Kapil Vatwani, Ishan Munje, Madhava Krishna, Nalesh Sivanandan, Nandhini Gopalan, Soumyendu Raha, S. K. Nandy, Ranjani Narayan
2015 J jnl
Scalable and Energy Efficient, Dynamically Reconfigurable Fast Fourier Transform Architecture.
J. Low Power Electron.
S. Kala, Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan
2014 J jnl
A framework for post-silicon realization of arbitrary instruction extensions on reconfigurable data-paths.
J. Syst. Archit.
Saptarsi Das, Kavitha T. Madhu, Madhav Krishna, Nalesh Sivanandan, Farhad Merchant, Santhi Natarajan, Ipsita Biswas, Adithya Pulli, S. K. Nandy, Ranjani Narayan
2014 — conf
Energy Efficient, Scalable, and Dynamically Reconfigurable FFT Architecture for OFDM Systems.
ISED
S. Kala, Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan
2014 — conf
Synthesis of Instruction Extensions on HyperCell, a reconfigurable datapath.
ICSAMOS
Kavitha T. Madhu, Saptarsi Das, Madhava Krishna C., Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan
2013 C conf
High throughput, low latency, memory optimized 64K point FFT architecture using novel radix-4 butterfly unit.
ISCAS
S. Kala, Nalesh Sivanandan, Arka Maity, S. K. Nandy, Ranjani Narayan