Najmi T. Jarwala

13 papers A 7Misc 1Journal 4Unranked 1
YearRankTypeTitle / Venue / Authors
1997 J jnl
Designing "Dual Personality" IEEE 1149.1 Compliant Multi-Chip Modules.
J. Electron. Test.
Najmi T. Jarwala
1996 J jnl
Built-In Self-Test: Assuring System Integrity.
Computer
Bernd Könemann, Ben Bennetts, Najmi T. Jarwala, Benoit Nadeau-Dostie
1996 Misc conf
Hardware-Software Co-Design for Test: It's the Last Straw!
VTS
J. El-Ziq, Najmi T. Jarwala, Niraj K. Jha, Peter Marwedel, Christos A. Papachristou, Janusz Rajski, John W. Sheppard
1996 — conf
Lessons Learned from Practical Applications of BIST/B-S Technology.
Asian Test Symposium
Najmi T. Jarwala, Paul W. Rutkowski, Shianling Wu, Chi W. Yau
1995 A conf
A Secure Data Transmission Scheme for 1149.1 Backplane Test Bus.
ITC
Wuudiann Ke, Duy Le, Najmi T. Jarwala
1994 A conf
Designing "Dual-Personality" IEEE 1149.1-Compliant Multi-Chip Modules.
ITC
Najmi T. Jarwala
1993 J jnl
A structured approach to board-level BIST using the boundary-scan master.
Microprocess. Microsystems
Najmi T. Jarwala, Chi W. Yau
1992 A conf
A Framework for Boundary-Scan Based System Test Diagnosis.
ITC
Najmi T. Jarwala, Paul Stiling, Enn Tammaru, Chi W. Yau
1991 A conf
Achieving Board-Level BIST Using the Boundary-Scan Master.
ITC
Najmi T. Jarwala, Chi W. Yau
1990 A conf
The boundary-scan master: target applications and functional requirements.
ITC
Chi W. Yau, Najmi T. Jarwala
1989 A conf
A New Framework for Analyzing Test Generation and Diagnosis Algorithms for Wiring Interconnects.
ITC
Najmi T. Jarwala, Chi W. Yau
1989 A conf
A Unified Theory for Designing Optimal Test Generation and Diagnosis Algorithms for Board Interconnects.
ITC
Najmi T. Jarwala, Chi W. Yau
1988 J jnl
TRAM: A Design Methodology for High-Performance, Easily Testable, Multimegabit RAM's.
IEEE Trans. Computers
Najmi T. Jarwala, Dhiraj K. Pradhan