Naifeng Jing - RankMe

145 papers A* 21A 14B 7C 15Journal 54Unranked 34

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	AGS: Accelerating 3D Gaussian Splatting SLAM via CODEC-Assisted Frame Covisibility Detection. ASPLOS (1) Houshu He, Naifeng Jing, Li Jiang, Xiaoyao Liang, Zhuoran Song
2026	J	`jnl`	Leveraging Tensor Dataflow for Improved Thermal Performance on 3D-Stacked SRAM Architecture. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Pengyu Liu, Liyan Chen, Zelong Yuan, Yingkun Liu, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing
2026	J	`jnl`	Signal integrity-aware multi-path design workflow for ultra-large-scale three-dimensional chips: A logic-on-memory stacking case study. Microelectron. J. Ang Li, Jianfei Jiang, Naifeng Jing, Yanan Sun, Zhigang Mao, Qin Wang
2026	—	`conf`	Viper: An ILP-Based Vectorization Framework for Fully Homomorphic Encryption. ASP-DAC Weidong Yang, Xinmo Li, Xiangmin Guo, Jianfei Jiang, Naifeng Jing, Qin Wang, Zhigang Mao, Weiguang Sheng
2025	J	`jnl`	A Hierarchical 3-D Physical Design Method for Ultralarge-Scale Logic-on-Memory CGRA Chip. IEEE Trans. Very Large Scale Integr. Syst. Zizheng Dong, Shuaipeng Li, Weijia Zhu, Ang Li, Qin Wang, Naifeng Jing, Weiguang Sheng, Jianfei Jiang, Zhigang Mao
2025	J	`jnl`	AGS: Accelerating 3D Gaussian Splatting SLAM via CODEC-Assisted Frame Covisibility Detection. CoRR Houshu He, Naifeng Jing, Li Jiang, Xiaoyao Liang, Zhuoran Song
2025	A*	`conf`	AsyncDIMM: Achieving Asynchronous Execution in DIMM-Based Near-Memory Processing. HPCA Liyan Chen, Dongxu Lyu, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing
2025	A*	`conf`	AttenPIM: Accelerating LLM Attention with Dual-mode GEMV in Processing-in-Memory. DAC Liyan Chen, Dongxu Lyu, Zhenyu Li, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing
2025	J	`jnl`	Bridge-NDP: Efficient Communication-Computation Overlap in Near Data Processing System. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Liyan Chen, Pengyu Liu, Dongxu Lyu, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing
2025	J	`jnl`	Efficient Die-to-Die Communication: UCIe Link Simulation and Optimization in a Chiplet-Based System. IEEE J. Emerg. Sel. Topics Circuits Syst. Kunyue Li, Shuaipeng Li, Xiaoyan Li, Zizheng Dong, Sai Gao, Jialei Sun, Naifeng Jing, Qin Wang, Guanghui He, Jianfei Jiang
2025	J	`jnl`	GCNTrain+: A Versatile and Efficient Accelerator for Graph Convolutional Neural Network Training. ACM Trans. Archit. Code Optim. Zhuoran Song, Jiabei Long, Li Jiang, Naifeng Jing, Xiaoyao Liang
2025	A*	`conf`	HEAT: NPU-NDP HEterogeneous Architecture for Transformer-Empowered Graph Neural Networks. MICRO Ruiyang Chen, Zhuoran Song, Yicheng Zheng, Zeyu Zhu, Gang Li, Naifeng Jing, Xiaoyao Liang, Haibing Guan
2025	A	`conf`	HEILP: An ILP-Based Scale Management Method for Homomorphic Encryption Compiler. DATE Weidong Yang, Shuya Ji, Jianfei Jiang, Naifeng Jing, Qin Wang, Zhigang Mao, Weiguang Sheng
2025	J	`jnl`	L3: DIMM-PIM Integrated Architecture and Coordination for Scalable Long-Context LLM Inference. CoRR Qingyuan Liu, Liyan Chen, Yanning Yang, Haocheng Wang, Dong Du, Zhigang Mao, Naifeng Jing, Yubin Xia, Haibo Chen
2025	A*	`conf`	LUT Tensor Core: A Software-Hardware Co-Design for LUT-Based Low-Bit LLM Inference. ISCA Zhiwen Mo, Lei Wang, Jianyu Wei, Zhichen Zeng, Shijie Cao, Lingxiao Ma, Naifeng Jing, Ting Cao, Jilong Xue, Fan Yang, Mao Yang
2025	J	`jnl`	MACS: A Multidomain Collaborative Adaptive Clock Scheme for Large-Scale Reconfigurable Dataflow Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shuya Ji, Weidong Yang, Jianfei Jiang, Naifeng Jing, Honglan Jiang, Zhigang Mao, Qin Wang
2025	—	`conf`	MDNMP: Metapath-Driven Software-Hardware Co-Design for HGNN Acceleration with Near-Memory Processing. ASP-DAC Liyan Chen, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing
2025	A*	`conf`	MHDiff: Memory- and Hardware-Efficient Diffusion Acceleration via Focal Pixel Aware Quantization. DAC Chunyu Qi, Xuhang Wang, Ruiyang Chen, Yuanzheng Yao, Naifeng Jing, Chen Zhang, Jun Wang, Zhihui Fu, Xiaoyao Liang, Zhuoran Song
2025	A*	`conf`	Principle-based Dataflow Optimization for Communication Lower Bound in Operator-Fused Tensor Accelerator. DAC Lei Xu, Chen Yin, Zelong Yuan, Weiguang Sheng, Jianfei Jiang, Qin Wang, Naifeng Jing
2025	J	`jnl`	RTSA: A Run-Through Sparse Attention Framework for Video Transformer. IEEE Trans. Computers Xuhang Wang, Zhuoran Song, Chunyu Qi, Fangxin Liu, Naifeng Jing, Li Jiang, Xiaoyao Liang
2025	C	`conf`	RVME: An Efficient Matrix Engine Design Based on Matrix Extension of RISC-V. ICCD Wanqi Chen, Weidong Yang, Yiming Guo, Jing Qiu, Renpei Wang, Jianfei Jiang, Naifeng Jing, Qin Wang
2025	—	`conf`	STAMP: Accelerating Second-Order DNN Training Via ReRAM-Based Processing-in-Memory Architecture. APPT Yilong Zhao, Fangxin Liu, Mingyu Gao, Xiaoyao Liang, Qidong Tang, Chengyang Gu, Tao Yang, Naifeng Jing, Li Jiang
2025	A*	`conf`	SynGPU: Synergizing CUDA and Bit-Serial Tensor Cores for Vision Transformer Acceleration on GPU. DAC Yuanzheng Yao, Chen Zhang, Chunyu Qi, Ruiyang Chen, Jun Wang, Zhihui Fu, Naifeng Jing, Xiaoyao Liang, Zhuoran Song
2024	J	`jnl`	3A-ReRAM: Adaptive Activation Accumulation in ReRAM-Based CNN Accelerator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zihan Zhang, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing
2024	C	`conf`	A 0.8-ps RMS Precision Period Jitter Measurement Circuit with Offset Reduction. ISCAS Lin Xie, Zizheng Dong, Jialei Sun, Sai Gao, Shuaipeng Li, Naifeng Jing, Qin Wang, Jianfei Jiang
2024	J	`jnl`	A Comprehensive Dataflow-Mapping Optimization for Fully Pipelined Execution in Spatial Programmable Architecture. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Pengyu Liu, Ang Li, Liyan Chen, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing
2024	C	`conf`	A Flexible and High-Precision Activation Function Unit Based on Equi-Error Partitioning Algorithm. ISCAS Zelong Yuan, Siwei Yuan, Pengyu Liu, Chen Yin, Lei Xu, Weiguang Sheng, Naifeng Jing
2024	J	`jnl`	A novel vehicle collision detection system: Integrating audio-visual fusion for enhanced performance. Expert Syst. Appl. Kunyue Li, Zhengji Zhao, Qixuan Cai, Qin Wang, Naifeng Jing, Zhigang Mao, Jianfei Jiang
2024	B	`conf`	Bridge-NDP: Achieving Efficient Communication-Computation Overlap in Near Data Processing with Bridge Architecture. ASPDAC Liyan Chen, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing
2024	—	`conf`	CMC: Video Transformer Acceleration via CODEC Assisted Matrix Condensing. ASPLOS (2) Zhuoran Song, Chunyu Qi, Fangxin Liu, Naifeng Jing, Xiaoyao Liang
2024	J	`jnl`	DeltaGNN: Accelerating Graph Neural Networks on Dynamic Graphs With Delta Updating. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chen Yin, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing
2024	C	`conf`	Early: An Importance-Aware Early Firing and Exit for SNN Acceleration. ICCD Xuan Zhang, Zhuoran Song, Peng Zhou, Xing Li, Xueyuan Liu, Xiaolong Lin, Zhezhi He, Li Jiang, Naifeng Jing, Xiaoyao Liang
2024	A*	`conf`	Enabling Multiple Tensor-wise Operator Fusion for Transformer Models on Spatial Accelerators. DAC Lei Xu, Zhiwen Mo, Qin Wang, Jianfei Jiang, Naifeng Jing
2024	J	`jnl`	Environmental Condition Aware Super-Resolution Acceleration Framework in Server-Client Hierarchies. ACM Trans. Archit. Code Optim. Zhuoran Song, Zhongkai Yu, Xinkai Song, Yifan Hao, Li Jiang, Naifeng Jing, Xiaoyao Liang
2024	J	`jnl`	Janus: A Flexible Processing-in-Memory Graph Accelerator Toward Sparsity. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xing Li, Zhuoran Song, Rachata Ausavarungnirun, Xiao Liu, Xueyuan Liu, Xuan Zhang, Xuhang Wang, Jiayao Ling, Gang Li, Naifeng Jing, Xiaoyao Liang
2024	J	`jnl`	LUT Tensor Core: Lookup Table Enables Efficient Low-Bit LLM Inference Acceleration. CoRR Zhiwen Mo, Lei Wang, Jianyu Wei, Zhichen Zeng, Shijie Cao, Lingxiao Ma, Naifeng Jing, Ting Cao, Jilong Xue, Fan Yang, Mao Yang
2024	J	`jnl`	RecPIM: Efficient In-Memory Processing for Personalized Recommendation Inference Using Near-Bank Architecture. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Weidong Yang, Yuqing Yang, Shuya Ji, Jianfei Jiang, Naifeng Jing, Qin Wang, Zhigang Mao, Weiguang Sheng
2024	B	`conf`	SparGNN: Efficient Joint Feature-Model Sparsity Exploitation in Graph Neural Network Acceleration. ASPDAC Chen Yin, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing
2024	A*	`conf`	UM-PIM: DRAM-based PIM with Uniform & Shared Memory Space. ISCA Yilong Zhao, Mingyu Gao, Fangxin Liu, Yiwei Hu, Zongwu Wang, Han Lin, Jin Li, He Xian, Hanlin Dong, Tao Yang, Naifeng Jing, Xiaoyao Liang, Li Jiang
2024	—	`conf`	VDA: A Simple but Efficient Virtual-Channel-Based Deadlock Avoidance Scheme for Scalable Chiplet Networks. ACM Great Lakes Symposium on VLSI Duo Yu, Ang Li, Naifeng Jing, Jianfei Jiang, Weiguang Sheng, Qin Wang
2024	—	`conf`	Watt: A Write-Optimized RRAM-Based Accelerator for Attention. Euro-Par (2) Xuan Zhang, Zhuoran Song, Xing Li, Zhezhi He, Naifeng Jing, Li Jiang, Xiaoyao Liang
2023	J	`jnl`	A Point Cloud Video Recognition Acceleration Framework Based on Tempo-Spatial Information. IEEE Trans. Parallel Distributed Syst. Zhuoran Song, Wanzhen Liu, Tao Yang, Fangxin Liu, Naifeng Jing, Xiaoyao Liang
2023	J	`jnl`	A Reschedulable Dataflow-SIMD Execution for Increased Utilization in CGRA Cross-Domain Acceleration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chen Yin, Naifeng Jing, Jianfei Jiang, Qin Wang, Zhigang Mao
2023	C	`conf`	ACET: An Adaptive Clock Scheme Exploiting Comprehensive Timing Slack for Reconfigurable Processors. ICCD Shuya Ji, Weidong Yang, Jianfei Jiang, Naifeng Jing, Weiguang Sheng, Ang Li, Qin Wang
2023	A*	`conf`	AdaS: A Fast and Energy-Efficient CNN Accelerator Exploiting Bit-Sparsity. DAC Xiaolong Lin, Gang Li, Zizhao Liu, Yadong Liu, Fan Zhang, Zhuoran Song, Naifeng Jing, Xiaoyao Liang
2023	—	`conf`	An Efficient near-Bank Processing Architecture for Personalized Recommendation System. ASP-DAC Yuqing Yang, Weidong Yang, Qin Wang, Naifeng Jing, Jianfei Jiang, Zhigang Mao, Weiguang Sheng
2023	—	`conf`	An NoC-based CNN Accelerator for Edge Computing. ASICON Jianing Gao, Qiming Shao, Fangyu Deng, Qin Wang, Naifeng Jing, Jianfei Jiang
2023	J	`jnl`	E ACM Trans. Design Autom. Electr. Syst. Zhuoran Song, Naifeng Jing, Xiaoyao Liang
2023	J	`jnl`	Exploiting bit sparsity in both activation and weight in neural networks accelerators. Integr. Naifeng Jing, Zihan Zhang, Yongshuai Sun, Pengyu Liu, Liyan Chen, Qin Wang, Jianfei Jiang
2023	—	`conf`	High-Performance Genomic Analysis Heterogeneous System Using OpenCL. ASICON Jianing Gao, Lingyi Liu, Qin Wang, Naifeng Jing, Jianfei Jiang
2023	C	`conf`	HyAcc: A Hybrid CAM-MAC RRAM-based Accelerator for Recommendation Model. ICCD Xuan Zhang, Zhuoran Song, Xing Li, Zhezhi He, Li Jiang, Naifeng Jing, Xiaoyao Liang
2023	—	`conf`	PRADA: Point Cloud Recognition Acceleration via Dynamic Approximation. ACM TUR-C Zhuoran Song, Naifeng Jing, Xiaoyao Liang
2023	A	`conf`	PRADA: Point Cloud Recognition Acceleration via Dynamic Approximation. DATE Zhuoran Song, Heng Lu, Gang Li, Li Jiang, Naifeng Jing, Xiaoyao Liang
2023	B	`conf`	Pipeline Balancing for Integrated Mapping in High Performance Spatial Programmable Architecture. FPL Pengyu Liu, Zihan Zhang, Chen Yin, Liyan Chen, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing
2023	—	`conf`	RTMDet-R2: An Improved Real-Time Rotated Object Detector. PRCV (12) Haifeng Xiang, Naifeng Jing, Jianfei Jiang, Hongbo Guo, Weiguang Sheng, Zhigang Mao, Qin Wang
2023	—	`conf`	ReMap: Reorder Mapping for Multi-level Uneven Distribution on Sparse ReRAM Accelerator. ASICON Zhuo Chen, Zihan Zhang, Jianfei Jiang, Weiguang Sheng, Qin Wang, Naifeng Jing
2023	J	`jnl`	Real-Time Video Recognition via Decoder-Assisted Neural Network Acceleration Framework. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zhuoran Song, Heng Lu, Li Jiang, Naifeng Jing, Xiaoyao Liang
2022	J	`jnl`	A Hybrid-Grained Remapping Defense Scheme Against Hard Failures for Row-Column-NVM. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Taozhong Li, Naifeng Jing, Zhigang Mao, Yiran Chen
2022	J	`jnl`	A Low Coupling and Lightweight Algorithm for Ship Detection in Optical Remote Sensing Images. IEEE Geosci. Remote. Sens. Lett. Guochao Deng, Qin Wang, Jianfei Jiang, Qirun Hong, Naifeng Jing, Weiguang Sheng, Zhigang Mao
2022	J	`jnl`	A Novel Architecture Design for Output Significance Aligned Flow with Adaptive Control in ReRAM-based Neural Network Accelerator. ACM Trans. Design Autom. Electr. Syst. Taozhong Li, Naifeng Jing, Jianfei Jiang, Qin Wang, Zhigang Mao, Yiran Chen
2022	J	`jnl`	A Universal RRAM-Based DNN Accelerator With Programmable Crossbars Beyond MVM Operator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zihan Zhang, Jianfei Jiang, Yongxin Zhu, Qin Wang, Zhigang Mao, Naifeng Jing
2022	J	`jnl`	An Efficient CNN Accelerator Using Inter-Frame Data Reuse of Videos on FPGAs. IEEE Trans. Very Large Scale Integr. Syst. Shengzhao Li, Qin Wang, Jianfei Jiang, Weiguang Sheng, Naifeng Jing, Zhigang Mao
2022	—	`conf`	Boosting ReRAM-based DNN by Row Activation Oversubscription. ASP-DAC Mengyu Guo, Zihan Zhang, Jianfei Jiang, Qin Wang, Naifeng Jing
2022	J	`jnl`	CP-ViT: Cascade Vision Transformer Pruning via Progressive Sparsity Prediction. CoRR Zhuoran Song, Yihong Xu, Zhezhi He, Li Jiang, Naifeng Jing, Xiaoyao Liang
2022	J	`jnl`	DNN Training Acceleration via Exploring GPGPU Friendly Sparsity. CoRR Zhuoran Song, Yihong Xu, Han Li, Naifeng Jing, Xiaoyao Liang, Li Jiang
2022	A*	`conf`	E DAC Zhuoran Song, Zhongkai Yu, Naifeng Jing, Xiaoyao Liang
2022	A*	`conf`	EBSP: evolving bit sparsity patterns for hardware-friendly inference of quantized deep neural networks. DAC Fangxin Liu, Wenbo Zhao, Zongwu Wang, Yongbiao Chen, Zhezhi He, Naifeng Jing, Xiaoyao Liang, Li Jiang
2022	C	`conf`	GCNTrain: A Unified and Efficient Accelerator for Graph Convolutional Neural Network Training. ICCD Heng Lu, Zhuoran Song, Xing Li, Naifeng Jing, Xiaoyao Liang
2022	A	`conf`	Gzippo: Highly-Compact Processing-in-Memory Graph Accelerator Alleviating Sparsity and Redundancy. ICCAD Xing Li, Rachata Ausavarungnirun, Xiao Liu, Xueyuan Liu, Xuan Zhang, Heng Lu, Zhuoran Song, Naifeng Jing, Xiaoyao Liang
2022	J	`jnl`	RePAST: A ReRAM-based PIM Accelerator for Second-order Training of DNN. CoRR Yilong Zhao, Li Jiang, Mingyu Gao, Naifeng Jing, Chengyang Gu, Qidong Tang, Fangxin Liu, Tao Yang, Xiaoyao Liang
2022	A*	`conf`	Ristretto: An Atomized Processing Architecture for Sparsity-Condensed Stream Flow in CNN. MICRO Gang Li, Weixiang Xu, Zhuoran Song, Naifeng Jing, Jian Cheng, Xiaoyao Liang
2021	J	`jnl`	A 3.85-Gb/s 8 × 8 Soft-Output MIMO Detector With Lattice-Reduction-Aided Channel Preprocessing. IEEE Trans. Very Large Scale Integr. Syst. Zhuojun Liang, Dongxu Lv, Chao Cui, Hai-Bao Chen, Weifeng He, Weiguang Sheng, Naifeng Jing, Zhigang Mao, Guanghui He
2021	—	`conf`	A Mapping Method for Reconfigurable Array based on Decoupled DataFlow. BigDataSecurity Zihan Zhang, Jianfei Jiang, Weiguang Sheng, Qin Wang, Zhigang Mao, Naifeng Jing
2021	—	`conf`	Exploiting Dynamic Bit Sparsity in Activation for Deep Neural Network Acceleration. ASICON Yongshuai Sun, Mengyu Guo, Dacheng Liang, Shan Tang, Naifeng Jing
2021	C	`conf`	Fast FPGA-Based Emulation for ReRAM-Enabled Deep Neural Network Accelerator. ISCAS Yongquan Shi, Yongshuai Sun, Jianfei Jiang, Guanghui He, Qin Wang, Naifeng Jing
2021	J	`jnl`	ITT-RNA: Imperfection Tolerable Training for RRAM-Crossbar-Based Deep Neural-Network Accelerator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zhuoran Song, Yanan Sun, Lerong Chen, Tianjian Li, Naifeng Jing, Xiaoyao Liang, Li Jiang
2021	—	`conf`	PIPArch: Programmable Image Processing Architecture Using Sliding Array. ISPA/BDCloud/SocialCom/SustainCom Feiyang Wu, Zhuoran Song, Jing Ke, Li Jiang, Naifeng Jing, Xiaoyao Liang
2021	—	`conf`	Re2PIM: A Reconfigurable ReRAM-Based PIM Design for Variable-Sized Vector-Matrix Multiplication. ACM Great Lakes Symposium on VLSI Yilong Zhao, Zhezhi He, Naifeng Jing, Xiaoyao Liang, Li Jiang
2021	J	`jnl`	SME: ReRAM-based Sparse-Multiplication-Engine to Squeeze-Out Bit Sparsity of Neural Network. CoRR Fangxin Liu, Wenbo Zhao, Yilong Zhao, Zongwu Wang, Tao Yang, Zhezhi He, Naifeng Jing, Xiaoyao Liang, Li Jiang
2021	A	`conf`	Subgraph Decoupling and Rescheduling for Increased Utilization in CGRA Architecture. DATE Chen Yin, Qin Wang, Jianfei Jiang, Weiguang Sheng, Guanghui He, Zhigang Mao, Naifeng Jing
2020	J	`jnl`	A Hierarchical Scrubbing Technique for SEU Mitigation on SRAM-Based FPGAs. IEEE Trans. Very Large Scale Integr. Syst. Guanghui He, Sijie Zheng, Naifeng Jing
2020	B	`conf`	A High-Throughput Tumor Location System with Deep Learning for Colorectal Cancer Histopathology Image. AIME Jing Ke, Yiqing Shen, Yi Guo, Jason D. Wright, Naifeng Jing, Xiaoyao Liang
2020	C	`conf`	A Low Power Temperature-Compensated Common-Mode Voltage Detector for Dynamic Amplifiers. ISCAS Ran Wang, Yuekang Guo, Jing Jin, Xiaoming Liu, Naifeng Jing, Jianjun Zhou
2020	B	`conf`	A Winograd-Based CNN Accelerator with a Fine-Grained Regular Sparsity Pattern. FPL Tao Yang, Yunkun Liao, Jianping Shi, Yun Liang, Naifeng Jing, Li Jiang
2020	A*	`conf`	DRQ: Dynamic Region-based Quantization for Deep Neural Network Acceleration. ISCA Zhuoran Song, Bangqi Fu, Feiyang Wu, Zhaoming Jiang, Li Jiang, Naifeng Jing, Xiaoyao Liang
2020	C	`conf`	Decoupling the Multi-Rate Dataflow Execution in Coarse-Grained Reconfigurable Array. ISCAS Tu Hong, Ning Guan, Chen Yin, Qin Wang, Jianfei Jiang, Jing Jin, Guanghui He, Naifeng Jing
2020	—	`conf`	Design of a Hardware Accelerator for Zero-Knowledge Proof in Blockchains. SmartCom B. O. Peng, Yongxin Zhu, Naifeng Jing, Xiaoying Zheng, Yueying Zhou
2020	—	`conf`	Enabling Resistive-RAM-based Activation Functions for Deep Neural Network Acceleration. ACM Great Lakes Symposium on VLSI Zihan Zhang, Taozhong Li, Ning Guan, Qin Wang, Guanghui He, Weiguang Sheng, Zhigang Mao, Naifeng Jing
2020	—	`conf`	FIMIL : A high-throughput deep learning model for abnormality detection with weak annotation in microscopy images. ACSW Jing Ke, Changchang Liu, Yizhou Lu, Naifeng Jing, Xiaoyao Liang, Fusong Jiang
2020	A*	`conf`	GPNPU: Enabling Efficient Hardware-Based Direct Convolution with Multi-Precision Support in GPU Tensor Cores. DAC Zhuoran Song, Jianfei Wang, Tianjian Li, Li Jiang, Jing Ke, Xiaoyao Liang, Naifeng Jing
2020	—	`conf`	Identifying patch-level MSI from histological images of Colorectal Cancer by a Knowledge Distillation Model. BIBM Jing Ke, Yiqing Shen, Jason D. Wright, Naifeng Jing, Xiaoyao Liang, Dinggang Shen
2020	—	`conf`	PRArch: Pattern-Based Reconfigurable Architecture for Deep Neural Network Acceleration. HPCC/DSS/SmartCity Zhaoming Jiang, Zhuoran Song, Xiaoyao Liang, Naifeng Jing
2020	J	`jnl`	Priority Branches for Ship Detection in Optical Remote Sensing Images. Remote. Sens. Yijia Zhang, Weiguang Sheng, Jianfei Jiang, Naifeng Jing, Qin Wang, Zhigang Mao
2020	—	`conf`	Reliable SoC Design and Implementation of SHA-3-HMAC Algorithm with Attack Protection. SmartCloud Tao Zhou, Yongxin Zhu, Naifeng Jing, Tianhao Nan, Wanyi Li, Bo Peng
2020	A*	`conf`	VR-DANN: Real-Time Video Recognition via Decoder-Assisted Neural Network Acceleration. MICRO Zhuoran Song, Feiyang Wu, Xueyuan Liu, Jing Ke, Naifeng Jing, Xiaoyao Liang
2019	J	`jnl`	A New Cellular-Based Redundant TSV Structure for Clustered Faults. IEEE Trans. Very Large Scale Integr. Syst. Qin Wang, Zechen Liu, Jianfei Jiang, Naifeng Jing, Weiguang Sheng
2019	J	`jnl`	A Novel Resistive Memory-based Process-in-memory Architecture for Efficient Logic and Add Operations. ACM Trans. Design Autom. Electr. Syst. Taozhong Li, Qin Wang, Yongxin Zhu, Jianfei Jiang, Guanghui He, Jing Jin, Zhigang Mao, Naifeng Jing
2019	C	`conf`	A Rapid Scrubbing Technique for SEU Mitigation on SRAM-Based FPGAs. ISCAS Sijie Zheng, Hongjun You, Guanghui He, Qin Wang, Tao Si, Jianfei Jiang, Jing Jin, Naifeng Jing
2019	—	`conf`	A sharing-aware L1.5D cache for data reuse in GPGPUs. ASP-DAC Jianfei Wang, Li Jiang, Jing Ke, Xiaoyao Liang, Naifeng Jing
2019	J	`jnl`	Energy-Efficient Nonvolatile SRAM Design Based on Resistive Switching Multi-Level Cells. IEEE Trans. Circuits Syst. II Express Briefs Yanan Sun, Jiawei Gu, Weifeng He, Qin Wang, Naifeng Jing, Zhigang Mao, Weikang Qian, Li Jiang
2019	J	`jnl`	Energy-Efficient and Quality-Assured Approximate Computing Framework Using a Co-Training Method. ACM Trans. Design Autom. Electr. Syst. Li Jiang, Zhuoran Song, Haiyue Song, Chengwen Xu, Qiang Xu, Naifeng Jing, Weifeng Zhang, Xiaoyao Liang
2019	—	`conf`	HUBPA: high utilization bidirectional pipeline architecture for neuromorphic computing. ASP-DAC Houxiang Ji, Li Jiang, Tianjian Li, Naifeng Jing, Jing Ke, Xiaoyao Liang
2019	J	`jnl`	Scale Adaptive Proposal Network for Object Detection in Remote Sensing Images. IEEE Geosci. Remote. Sens. Lett. Shuo Zhang, Guanghui He, Hai-Bao Chen, Naifeng Jing, Qin Wang
2018	A	`conf`	A FPGA Friendly Approximate Computing Framework with Hybrid Neural Networks: (Abstract Only). FPGA Haiyue Song, Xiang Song, Tianjian Li, Hao Dong, Naifeng Jing, Xiaoyao Liang, Li Jiang
2018	J	`jnl`	AXNet: ApproXimate computing using an end-to-end trainable neural network. CoRR Zhenghao Peng, Xuyang Chen, Chengwen Xu, Naifeng Jing, Xiaoyao Liang, Cewu Lu, Li Jiang
2018	A	`conf`	AXNet: approximate computing using an end-to-end trainable neural network. ICCAD Zhenghao Peng, Xuyang Chen, Chengwen Xu, Naifeng Jing, Xiaoyao Liang, Cewu Lu, Li Jiang
2018	J	`jnl`	CNFET-Based High Throughput SIMD Architecture. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Li Jiang, Tianjian Li, Naifeng Jing, Nam Sung Kim, Minyi Guo, Xiaoyao Liang
2018	J	`jnl`	IBOM: An Integrated and Balanced On-Chip Memory for High Performance GPGPUs. IEEE Trans. Parallel Distributed Syst. Jianfei Wang, Qin Wang, Li Jiang, Chao Li, Xiaoyao Liang, Naifeng Jing
2018	J	`jnl`	Invocation-driven Neural Approximate Computing with a Multiclass-Classifier and Multiple Approximators. CoRR Haiyue Song, Chengwen Xu, Qiang Xu, Zhuoran Song, Naifeng Jing, Xiaoyao Liang, Li Jiang
2018	A	`conf`	Invocation-driven neural approximate computing with a multiclass-classifier and multiple approximators. ICCAD Haiyue Song, Chengwen Xu, Qiang Xu, Zhuoran Song, Naifeng Jing, Xiaoyao Liang, Li Jiang
2017	J	`jnl`	A 0.33 V 2.5 μW cross-point data-aware write structure, read-half-select disturb-free sub-threshold SRAM in 130 nm CMOS. Integr. Wei Jin, Weifeng He, Jianfei Jiang, Haichao Huang, Xuejun Zhao, Yanan Sun, Xin Chen, Naifeng Jing
2017	—	`conf`	A wideband simplified transformer-based VCO with digital amplitude calibration. MWSCAS Xinchi Gao, Licheng Xu, Jing Jin, Naifeng Jing, Jianjun Zhou
2017	J	`jnl`	Bank Stealing for a Compact and Efficient Register File Architecture in GPGPU. IEEE Trans. Very Large Scale Integr. Syst. Naifeng Jing, Shunning Jiang, Shuang Chen, Jingjie Zhang, Li Jiang, Chao Li, Xiaoyao Liang
2017	J	`jnl`	Incorporating selective victim cache into GPGPU for high-performance computing. Concurr. Comput. Pract. Exp. Jianfei Wang, Fengfeng Fan, Li Jiang, Xiaoyao Liang, Naifeng Jing
2017	A*	`conf`	On Quality Trade-off Control for Approximate Computing Using Iterative Training. DAC Chengwen Xu, Xiangyu Wu, Wenqi Yin, Qiang Xu, Naifeng Jing, Xiaoyao Liang, Li Jiang
2017	A*	`conf`	Sneak-Path Based Test and Diagnosis for 1R RRAM Crossbar Using Voltage Bias Technique. DAC Tianjian Li, Xiangyu Bi, Naifeng Jing, Xiaoyao Liang, Li Jiang
2016	J	`jnl`	A Novel Test Method for Metallic CNTs in CNFET-Based SRAMs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tianjian Li, Feng Xie, Xiaoyao Liang, Qiang Xu, Krishnendu Chakrabarty, Naifeng Jing, Li Jiang
2016	C	`conf`	Applying Victim Cache in High Performance GPGPU Computing. ISPDC Fengfeng Fan, Jianfei Wang, Li Jiang, Xiaoyao Liang, Naifeng Jing
2016	C	`conf`	CNFET-based high throughput register file architecture. ICCD Tianjian Li, Li Jiang, Naifeng Jing, Nam Sung Kim, Xiaoyao Liang
2016	A*	`conf`	Cache-emulated register file: An integrated on-chip memory architecture for high performance GPGPUs. MICRO Naifeng Jing, Jianfei Wang, Fengfeng Fan, Wenkang Yu, Li Jiang, Chao Li, Xiaoyao Liang
2016	—	`conf`	Enabling in-situ logic-in-memory capability using resistive-RAM crossbar memory. FPT Naifeng Jing, Taozhong Li, Zhongyuan Zhao, Wei Jin, Yanan Sun, Weifeng He, Zhigang Mao
2016	J	`jnl`	Energy-Efficient eDRAM-Based On-Chip Storage Architecture for GPGPUs. IEEE Trans. Computers Naifeng Jing, Li Jiang, Tao Zhang, Chao Li, Fengfeng Fan, Xiaoyao Liang
2015	A	`conf`	Bank stealing for conflict mitigation in GPGPU Register File. ISLPED Naifeng Jing, Shuang Chen, Shunning Jiang, Li Jiang, Chao Li, Xiaoyao Liang
2015	J	`jnl`	Buddy SM: Sharing Pipeline Front-End for Improved Energy Efficiency in GPGPUs. ACM Trans. Archit. Code Optim. Tao Zhang, Naifeng Jing, Kaiming Jiang, Wei Shu, Min-You Wu, Xiaoyao Liang
2015	A	`conf`	CGSharing: Efficient content sharing in GPU-based cloud gaming. ISLPED Xiangyu Wu, Yuanfang Xia, Naifeng Jing, Xiaoyao Liang
2015	A*	`conf`	Jump test for metallic CNTs in CNFET-based SRAM. DAC Feng Xie, Xiaoyao Liang, Qiang Xu, Krishnendu Chakrabarty, Naifeng Jing, Li Jiang
2015	A	`conf`	On diagnosable and tunable 3D clock network design for lifetime reliability enhancement. ITC Li Jiang, Pu Pang, Naifeng Jing, Sung Kyu Lim, Xiaoyao Liang, Qiang Xu
2015	A	`conf`	Redundancy based Interconnect Duplication to Mitigate Soft Errors in SRAM-based FPGAs. ICCAD Naifeng Jing, Jiacheng Zhou, Jianfei Jiang, Xin Chen, Weifeng He, Zhigang Mao
2015	—	`conf`	Resource-saving compile flow for coarse-grained reconfigurable architectures. ReConFig Zhongyuan Zhao, Weiguang Sheng, Naifeng Jing, Weifeng He, Zhigang Mao
2015	—	`conf`	Timing-driven placement for carbon nanotube circuits. SoCC Chen Wang, Li Jiang, Shiyan Hu, Tianjian Li, Xiaoyao Liang, Naifeng Jing, Weikang Qian
2014	J	`jnl`	IPF: In-Place X-Filling Algorithm for the Reliability of Modern FPGAs. IEEE Trans. Very Large Scale Integr. Syst. Zhe Feng, Naifeng Jing, Lei He
2013	A*	`conf`	An energy-efficient and scalable eDRAM-based register file architecture for GPGPU. ISCA Naifeng Jing, Yao Shen, Yao Lu, Shrikanth Ganapathy, Zhigang Mao, Minyi Guo, Ramon Canal, Xiaoyao Liang
2013	A	`conf`	Compiler assisted dynamic register file in GPGPU. ISLPED Naifeng Jing, Haopeng Liu, Yao Lu, Xiaoyao Liang
2012	—	`conf`	Contention and energy aware mapping for real-time applications on Network-on-Chip. ISOCC Bingjing Ge, Naifeng Jing, Weifeng He, Zhigang Mao
2012	—	`conf`	Heterogeneous configuration memory scrubbing for soft error mitigation in FPGAs. FPT Ju-Yueh Lee, Cheng-Ru Chang, Naifeng Jing, Juexiao Su, Shi-Jie Wen, Rick Wong, Lei He
2012	J	`jnl`	SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithms. ACM Trans. Design Autom. Electr. Syst. Naifeng Jing, Ju-Yueh Lee, Zhe Feng, Weifeng He, Zhigang Mao, Lei He
2011	C	`conf`	A general statistical estimation for application mapping in Network-on-Chip. VLSI-SoC Naifeng Jing, Weifeng He, Zhigang Mao
2011	C	`conf`	A thermal-aware task mapping flow for coarse-grain dynamic reconfigurable processor. ISCAS Li Xie, Weifeng He, Naifeng Jing, Zhigang Mao
2011	A	`conf`	Fault modeling and characteristics of SRAM-based FPGAs (abstract only). FPGA Naifeng Jing, Ju-Yueh Lee, Chun Zhang, Jiarong Tong, Zhigang Mao, Lei He
2011	B	`conf`	IPF: In-Place X-Filling to Mitigate Soft Errors in SRAM-Based FPGAs. FPL Zhe Feng, Naifeng Jing, Gengsheng Chen, Yu Hu, Lei He
2011	A	`conf`	Mitigating FPGA interconnect soft errors by in-place LUT inversion. ICCAD Naifeng Jing, Ju-Yueh Lee, Weifeng He, Zhigang Mao, Lei He
2011	B	`conf`	Quantitative SEU Fault Evaluation for SRAM-Based FPGA Architectures and Synthesis Algorithms. FPL Naifeng Jing, Ju-Yueh Lee, Zhe Feng, Weifeng He, Zhigang Mao, Shi-Jie Wen, Rick Wong, Lei He
2010	—	`conf`	Resource constrained mapping of data flow graphs onto coarse-grained reconfigurable array. SoCC Naifeng Jing, Weifeng He, Zhigang Mao
2010	J	`jnl`	Statistical estimation and evaluation for communication mapping in Network-on-Chip. Integr. Naifeng Jing, Weifeng He, Yongxin Zhu, Zhigang Mao
2009	—	`conf`	Statistical Estimation for Total Communication Load in Application-Specific Network-on-Chip. ICESS Naifeng Jing, Zhigang Mao, Yongxin Zhu