| Year | Rank | Type | Title / Venue / Authors |
|---|---|---|---|
| 2026 | — | conf |
ASPLOS (1)
|
| 2026 | J | jnl |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
|
| 2026 | J | jnl |
Microelectron. J.
|
| 2026 | — | conf |
ASP-DAC
|
| 2025 | J | jnl |
IEEE Trans. Very Large Scale Integr. Syst.
|
| 2025 | J | jnl |
CoRR
|
| 2025 | A* | conf |
HPCA
|
| 2025 | A* | conf |
DAC
|
| 2025 | J | jnl |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
|
| 2025 | J | jnl |
Efficient Die-to-Die Communication: UCIe Link Simulation and Optimization in a Chiplet-Based System.
IEEE J. Emerg. Sel. Topics Circuits Syst.
|
| 2025 | J | jnl |
ACM Trans. Archit. Code Optim.
|
| 2025 | A* | conf |
MICRO
|
| 2025 | A | conf |
DATE
|
| 2025 | J | jnl |
CoRR
|
| 2025 | A* | conf |
ISCA
|
| 2025 | J | jnl |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
|
| 2025 | — | conf |
ASP-DAC
|
| 2025 | A* | conf |
DAC
|
| 2025 | A* | conf |
DAC
|
| 2025 | J | jnl |
IEEE Trans. Computers
|
| 2025 | C | conf |
ICCD
|
| 2025 | — | conf |
APPT
|
| 2025 | A* | conf |
DAC
|
| 2024 | J | jnl |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
|
| 2024 | C | conf |
ISCAS
|
| 2024 | J | jnl |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
|
| 2024 | C | conf |
ISCAS
|
| 2024 | J | jnl |
Expert Syst. Appl.
|
| 2024 | B | conf |
ASPDAC
|
| 2024 | — | conf |
ASPLOS (2)
|
| 2024 | J | jnl |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
|
| 2024 | C | conf |
ICCD
|
| 2024 | A* | conf |
DAC
|
| 2024 | J | jnl |
ACM Trans. Archit. Code Optim.
|
| 2024 | J | jnl |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
|
| 2024 | J | jnl |
CoRR
|
| 2024 | J | jnl |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
|
| 2024 | B | conf |
ASPDAC
|
| 2024 | A* | conf |
ISCA
|
| 2024 | — | conf |
ACM Great Lakes Symposium on VLSI
|
| 2024 | — | conf |
Euro-Par (2)
|
| 2023 | J | jnl |
IEEE Trans. Parallel Distributed Syst.
|
| 2023 | J | jnl |
A Reschedulable Dataflow-SIMD Execution for Increased Utilization in CGRA Cross-Domain Acceleration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
|
| 2023 | C | conf |
ICCD
|
| 2023 | A* | conf |
DAC
|
| 2023 | — | conf |
ASP-DAC
|
| 2023 | — | conf |
ASICON
|
| 2023 | J | jnl |
ACM Trans. Design Autom. Electr. Syst.
|
| 2023 | J | jnl |
Integr.
|
| 2023 | — | conf |
ASICON
|
| 2023 | C | conf |
ICCD
|
| 2023 | — | conf |
ACM TUR-C
|
| 2023 | A | conf |
DATE
|
| 2023 | B | conf |
FPL
|
| 2023 | — | conf |
PRCV (12)
|
| 2023 | — | conf |
ASICON
|
| 2023 | J | jnl |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
|
| 2022 | J | jnl |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
|
| 2022 | J | jnl |
IEEE Geosci. Remote. Sens. Lett.
|
| 2022 | J | jnl |
ACM Trans. Design Autom. Electr. Syst.
|
| 2022 | J | jnl |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
|
| 2022 | J | jnl |
IEEE Trans. Very Large Scale Integr. Syst.
|
| 2022 | — | conf |
ASP-DAC
|
| 2022 | J | jnl |
CoRR
|
| 2022 | J | jnl |
CoRR
|
| 2022 | A* | conf |
DAC
|
| 2022 | A* | conf |
DAC
|
| 2022 | C | conf |
ICCD
|
| 2022 | A | conf |
ICCAD
|
| 2022 | J | jnl |
CoRR
|
| 2022 | A* | conf |
MICRO
|
| 2021 | J | jnl |
IEEE Trans. Very Large Scale Integr. Syst.
|
| 2021 | — | conf |
BigDataSecurity
|
| 2021 | — | conf |
ASICON
|
| 2021 | C | conf |
ISCAS
|
| 2021 | J | jnl |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
|
| 2021 | — | conf |
ISPA/BDCloud/SocialCom/SustainCom
|
| 2021 | — | conf |
ACM Great Lakes Symposium on VLSI
|
| 2021 | J | jnl |
CoRR
|
| 2021 | A | conf |
DATE
|
| 2020 | J | jnl |
IEEE Trans. Very Large Scale Integr. Syst.
|
| 2020 | B | conf |
AIME
|
| 2020 | C | conf |
ISCAS
|
| 2020 | B | conf |
FPL
|
| 2020 | A* | conf |
ISCA
|
| 2020 | C | conf |
ISCAS
|
| 2020 | — | conf |
SmartCom
|
| 2020 | — | conf |
ACM Great Lakes Symposium on VLSI
|
| 2020 | — | conf |
ACSW
|
| 2020 | A* | conf |
DAC
|
| 2020 | — | conf |
BIBM
|
| 2020 | — | conf |
HPCC/DSS/SmartCity
|
| 2020 | J | jnl |
Remote. Sens.
|
| 2020 | — | conf |
SmartCloud
|
| 2020 | A* | conf |
MICRO
|
| 2019 | J | jnl |
IEEE Trans. Very Large Scale Integr. Syst.
|
| 2019 | J | jnl |
ACM Trans. Design Autom. Electr. Syst.
|
| 2019 | C | conf |
ISCAS
|
| 2019 | — | conf |
ASP-DAC
|
| 2019 | J | jnl |
IEEE Trans. Circuits Syst. II Express Briefs
|
| 2019 | J | jnl |
ACM Trans. Design Autom. Electr. Syst.
|
| 2019 | — | conf |
ASP-DAC
|
| 2019 | J | jnl |
IEEE Geosci. Remote. Sens. Lett.
|
| 2018 | A | conf |
FPGA
|
| 2018 | J | jnl |
CoRR
|
| 2018 | A | conf |
ICCAD
|
| 2018 | J | jnl |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
|
| 2018 | J | jnl |
IEEE Trans. Parallel Distributed Syst.
|
| 2018 | J | jnl |
CoRR
|
| 2018 | A | conf |
ICCAD
|
| 2017 | J | jnl |
Integr.
|
| 2017 | — | conf |
MWSCAS
|
| 2017 | J | jnl |
IEEE Trans. Very Large Scale Integr. Syst.
|
| 2017 | J | jnl |
Concurr. Comput. Pract. Exp.
|
| 2017 | A* | conf |
DAC
|
| 2017 | A* | conf |
DAC
|
| 2016 | J | jnl |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
|
| 2016 | C | conf |
ISPDC
|
| 2016 | C | conf |
ICCD
|
| 2016 | A* | conf |
Cache-emulated register file: An integrated on-chip memory architecture for high performance GPGPUs.
MICRO
|
| 2016 | — | conf |
FPT
|
| 2016 | J | jnl |
IEEE Trans. Computers
|
| 2015 | A | conf |
ISLPED
|
| 2015 | J | jnl |
ACM Trans. Archit. Code Optim.
|
| 2015 | A | conf |
ISLPED
|
| 2015 | A* | conf |
DAC
|
| 2015 | A | conf |
ITC
|
| 2015 | A | conf |
ICCAD
|
| 2015 | — | conf |
ReConFig
|
| 2015 | — | conf |
SoCC
|
| 2014 | J | jnl |
IEEE Trans. Very Large Scale Integr. Syst.
|
| 2013 | A* | conf |
ISCA
|
| 2013 | A | conf |
ISLPED
|
| 2012 | — | conf |
ISOCC
|
| 2012 | — | conf |
FPT
|
| 2012 | J | jnl |
SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithms.
ACM Trans. Design Autom. Electr. Syst.
|
| 2011 | C | conf |
VLSI-SoC
|
| 2011 | C | conf |
ISCAS
|
| 2011 | A | conf |
FPGA
|
| 2011 | B | conf |
FPL
|
| 2011 | A | conf |
ICCAD
|
| 2011 | B | conf |
FPL
|
| 2010 | — | conf |
SoCC
|
| 2010 | J | jnl |
Integr.
|
| 2009 | — | conf |
ICESS
|