Nagu R. Dhanwada

24 papers A* 2A 4C 2Misc 7Journal 4Unranked 5
YearRankTypeTitle / Venue / Authors
2021 A* conf
Energy Efficiency Boost in the AI-Infused POWER10 Processor.
ISCA
Brian W. Thompto, Dung Q. Nguyen, José E. Moreira, Ramon Bertran, Hans M. Jacobson, Richard J. Eickemeyer, Rahul M. Rao, Michael Goulet, Marcy Byers, Christopher J. Gonzalez, Karthik Swaminathan, Nagu R. Dhanwada, Silvia M. Müller, Andreas Wagner, Satish Kumar Sadasivam, Robert K. Montoye, William J. Starke, Christian G. Zoellin, Michael S. Floyd, Jeffrey Stuecheli, Nandhini Chandramoorthy, John-David Wellman, Alper Buyuktosunoglu, Matthias Pflanz, Balaram Sinharoy, Pradip Bose
2019 Misc conf
Heterogeneity Aware Power Abstraction for Hierarchical Power Analysis.
VLSID
Arun Joseph, Spandana Rachamalla, Shashidhar Reddy, Nagu R. Dhanwada
2014 Misc conf
Process Synchronization in Multi-core Systems Using On-Chip Memories.
VLSID
Arun Joseph, Nagu R. Dhanwada
2014 A conf
Towards a standard flow for system level power modeling.
ICCAD
Nagu R. Dhanwada, William Rhett Davis, Jerry Frenkil
2013 A conf
Efficient PVT independent abstraction of large IP blocks for hierarchical power analysis.
ICCAD
Nagu R. Dhanwada, David J. Hathaway, Victor V. Zyuban, Peng Peng, Karl Moody, William W. Dungan, Arun Joseph, Rahul M. Rao, Christopher J. Gonzalez
2012 J jnl
Leakage Power Contributor Modeling.
IEEE Des. Test Comput.
Nagu R. Dhanwada, David J. Hathaway, Jerry Frenkil, W. Rhett Davis, Harun Demircioglu
2008 — conf
Exploring power management in multi-core systems.
ASP-DAC
Reinaldo A. Bergamaschi, Guoling Han, Alper Buyuktosunoglu, Hiren D. Patel, Indira Nair, Gero Dittmann, Geert Janssen, Nagu R. Dhanwada, Zhigang Hu, Pradip Bose, John A. Darringer
2007 Misc conf
Performance modeling for early analysis of multi-core systems.
CODES+ISSS
Reinaldo A. Bergamaschi, Indira Nair, Gero Dittmann, Hiren D. Patel, Geert Janssen, Nagu R. Dhanwada, Alper Buyuktosunoglu, Emrah Acar, Gi-Joon Nam, Dorothy Kucar, Pradip Bose, John A. Darringer, Guoling Han
2006 J jnl
Hierarchical constraint transformation based on genetic optimization for analog system synthesis.
Integr.
Nagu R. Dhanwada, Alex Doboli, Adrián Núñez-Aldana, Ranga Vemuri
2006 — conf
Transaction Level Error Susceptibility Model for Bus Based SoC Architectures.
ISQED
Ing-Chao Lin, Suresh Srinivasan, Narayanan Vijaykrishnan, Nagu R. Dhanwada
2005 Misc conf
A power estimation methodology for systemC transaction level models.
CODES+ISSS
Nagu R. Dhanwada, Ing-Chao Lin, Vijaykrishnan Narayanan
2005 C conf
Temperature-Aware Voltage Islands Architecting in System-on-Chip Design.
ICCD
Wei-Lun Hung, Greg M. Link, Yuan Xie, Narayanan Vijaykrishnan, Nagu R. Dhanwada, John Conner
2005 J jnl
Transaction-level modeling for architectural and power analysis of PowerPC and CoreConnect-based systems.
Des. Autom. Embed. Syst.
Nagu R. Dhanwada, Reinaldo A. Bergamaschi, William W. Dungan, Indira Nair, Paul Gramann, William E. Dougherty, Ing-Chao Lin
2004 J jnl
A two-layer library-based approach to synthesis of analog systems from VHDL-AMS specifications.
ACM Trans. Design Autom. Electr. Syst.
Alex Doboli, Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri
2004 A conf
Architecting voltage islands in core-based system-on-a-chip designs.
ISLPED
Jingcao Hu, Youngsoo Shin, Nagu R. Dhanwada, Radu Marculescu
2003 — conf
Design topology aware physical metrics for placement analysis.
ACM Great Lakes Symposium on VLSI
Shyam Ramji, Nagu R. Dhanwada
2003 Misc conf
SEAS: a system for early analysis of SoCs.
CODES+ISSS
Reinaldo A. Bergamaschi, Youngsoo Shin, Nagu R. Dhanwada, Subhrajit Bhattacharya, William E. Dougherty, Indira Nair, John A. Darringer, Sarala Paliwal
2000 C conf
A heuristic technique for system-level architecture generation from signal-flow graph representations of analog systems.
ISCAS
Alex Doboli, Nagu R. Dhanwada, Ranga Vemuri
1999 — conf
A genetic approach to simultaneous parameter space exploration and constraint transformation in analog synthesis.
ISCAS (6)
Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri
1999 — conf
Automatic Constraint Transformation with Integrated Parameter Space Exploration in Analog System Synthesis.
ASP-DAC
Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri
1999 A* conf
Behavioral Synthesis of Analog Systems Using Two-layered Design Space Exploration.
DAC
Alex Doboli, Adrián Núñez-Aldana, Nagu R. Dhanwada, Sree Ganesan, Ranga Vemuri
1999 Misc conf
Component Characterization and Constraint Transformation Based on Directed Intervals for Analog Synthesis.
VLSI Design
Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri
1999 A conf
Hierarchical Constraint Transformation Using Directed Interval Search for Analog System Synthesis.
DATE
Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri
1998 Misc conf
Constraint Allocation in Analog System Synthesis.
VLSI Design
Nagu R. Dhanwada, Ranga Vemuri