Nagisa Ishiura

37 papers A* 7A 2C 6Journal 12Unranked 10
YearRankTypeTitle / Venue / Authors
2024 — conf
Enumeration of Genaralized Parallel Counters for Multi-Input Adder Synthesis for FPGAs.
APCCAS
Mugi Noda, Nagisa Ishiura
2021 C conf
Full Hardware Implementation of FreeRTOS-Based Real-Time Systems.
TENCON
Wakako Nakano, Yukino Shinohara, Nagisa Ishiura
2018 — conf
Extending equivalence transformation based program generator for random testing of C compilers.
A-TEST@ESEC/SIGSOFT FSE
Shogo Takakura, Mitsuyoshi Iwatsuji, Nagisa Ishiura
2018 — conf
Random testing of compilers' performance based on mixed static and dynamic code comparison.
A-TEST@ESEC/SIGSOFT FSE
Kota Kitaura, Nagisa Ishiura
2018 C conf
Synthesis of Full Hardware Implementation of RTOS-Based Systems.
RSP
Yuuki Oosako, Nagisa Ishiura, Hiroyuki Tomiyama, Hiroyuki Kanbara
2017 C conf
Binary synthesis implementing external interrupt handler as independent module.
RSP
Naoya Ito, Yuuki Oosako, Nagisa Ishiura, Hiroyuki Kanbara, Hiroyuki Tomiyama
2017 J jnl
CF3: Test Suite for Arithmetic Optimization of C Compilers.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yusuke Hibino, Hirofumi Ikeo, Nagisa Ishiura
2017 — conf
Distributed memory architecture for high-level synthesis of embedded controllers from Erlang.
Erlang Workshop
Kagumi Azuma, Nagisa Ishiura, Nobuaki Yoshida, Hiroyuki Kanbara
2017 C conf
Speculative execution in distributed controllers for high-level synthesis.
RSP
Miho Shimizu, Nagisa Ishiura, Sayuri Ota, Wakako Nakano
2016 J jnl
Detecting Arithmetic Optimization Opportunities for C Compilers by Randomly Generated Equivalent Programs.
IPSJ Trans. Syst. LSI Des. Methodol.
Atsushi Hashimoto, Nagisa Ishiura
2016 — conf
Random testing of C compilers based on test program generation by equivalence transformation.
APCCAS
Kazuhiro Nakamura, Nagisa Ishiura
2016 — conf
Reverse Engineering from Mainframe Assembly to C Codes in Legacy Migration.
IIAI-AAI
Daisuke Fujiwara, Nagisa Ishiura, Ryo Sakai, Ryo Aoki, Takashi Ogawara
2014 J jnl
Reinforcing Random Testing of Arithmetic Optimization of C Compilers by Scaling up Size and Number of Expressions.
Inf. Media Technol.
Eriko Nagai, Atsushi Hashimoto, Nagisa Ishiura
2014 J jnl
Reinforcing Random Testing of Arithmetic Optimization of C Compilers by Scaling up Size and Number of Expressions.
IPSJ Trans. Syst. LSI Des. Methodol.
Eriko Nagai, Atsushi Hashimoto, Nagisa Ishiura
2010 J jnl
Advantage and Possibility of Application-domain Specific Instruction-set Processor (ASIP).
Inf. Media Technol.
Masaharu Imai, Yoshinori Takeuchi, Keishi Sakanushi, Nagisa Ishiura
2010 J jnl
Advantage and Possibility of Application-domain Specific Instruction-set Processor (ASIP).
IPSJ Trans. Syst. LSI Des. Methodol.
Masaharu Imai, Yoshinori Takeuchi, Keishi Sakanushi, Nagisa Ishiura
2010 J jnl
Software Development Tool Generation Method Suitable for Instruction Set Extension of Embedded Processors.
IPSJ Trans. Syst. LSI Des. Methodol.
Takahiro Kumura, Soichiro Taga, Nagisa Ishiura, Yoshinori Takeuchi, Masaharu Imai
2008 J jnl
High-Level Synthesis of Software Function Calls.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Masanari Nishimura, Nagisa Ishiura, Yoshiyuki Ishimori, Hiroyuki Kanbara, Hiroyuki Tomiyama
2008 J jnl
Special Section on VLSI Design and CAD Algorithms.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Nagisa Ishiura
2002 — conf
Datapath oriented codesign method of application specific DSPs using retargetable compiler.
APCCAS (1)
Nagisa Ishiura, Tatsuo Watanabe
2000 — conf
Thread partitioning method for hardware compiler bach.
ASP-DAC
Mizuki Takahashi, Nagisa Ishiura, Akihisa Yamada, Takashi Kambe
1998 — conf
Binding and Scheduling Algorithms for Highly Retargetable Compilation.
ASP-DAC
Masayuki Yamaguchi, Nagisa Ishiura, Takashi Kambe
1995 C conf
Optimal Scheduling for Conditional Recource Sharing.
ISCAS
Akihisa Yamada, Satoru Nakamura, Nagisa Ishiura, Isao Shirakawa, Takashi Kambe
1994 J jnl
Fault simulation for multiple faults by Boolean function manipulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Noriyuki Takahashi, Nagisa Ishiura, Shuzo Yajima
1992 — conf
Linear time fault simulation algorithm using a content addressable memory.
EURO-DAC
Nagisa Ishiura, Shuzo Yajima
1991 A* conf
Breadth-First Manipulation of SBDD of Boolean Functions for Vector Processing.
DAC
Hiroyuki Ochi, Nagisa Ishiura, Shuzo Yajima
1991 A conf
Fault Simulation for Multiple Faults Using Shared BDD Representation of Fault Sets.
ICCAD
Noriyuki Takahashi, Nagisa Ishiura, Shuzo Yajima
1991 A conf
Minimazation of Binary Decision Diagrams Based on Exchanges of Variables.
ICCAD
Nagisa Ishiura, Hiroshi Sawada, Shuzo Yajima
1991 A* conf
Probabilistic CTSS: Analysis of Timing Error Probability in Asynchronous Logic Circuits.
DAC
Yutaka Deguchi, Nagisa Ishiura, Shuzo Yajima
1990 A* conf
Coded Time-Symbolic Simulation Using Shared Binary Decision Diagram.
DAC
Nagisa Ishiura, Yutaka Deguchi, Shuzo Yajima
1990 J jnl
Dynamic two-dimensional parallel simulation technique for high-speed fault simulation on a vector processor.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Nagisa Ishiura, Masayuki Ito, Shuzo Yajima
1990 C conf
Formal semantics of UDL/I and its applications to CAD/DA tools.
ICCD
Hiroto Yasuura, Nagisa Ishiura
1990 A* conf
NES: The Behavioral Model for the Formal Semantics of a Hardware Design Language UDL/I.
DAC
Nagisa Ishiura, Hiroto Yasuura, Shuzo Yajima
1990 A* conf
Shared Binary Decision Diagram with Attributed Edges for Efficient Boolean function Manipulation.
DAC
Shin-ichi Minato, Nagisa Ishiura, Shuzo Yajima
1989 A* conf
Semantics of a Hardware Design Language for Japanese Standardization.
DAC
Hiroto Yasuura, Nagisa Ishiura
1989 A* conf
Time-Symbolic Simulation for Accurate Timing Verification of Asynchronous Behavior of Logic Circuits.
DAC
Nagisa Ishiura, Mizuki Takahashi, Shuzo Yajima
1987 J jnl
High-Speed Logic Simulation on Vector Processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Nagisa Ishiura, Hiroto Yasuura, Shuzo Yajima